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参数资料
| 型号： | M68AW127BM70NK1T |
| 厂商： | 意法半导体 |
| 英文描述： | RES NET C-ARRY 10K 5% BUS |
| 中文描述： | 1Mbit的128K的× 8，3.0V异步SRAM |
| 文件页数： | 8/20页 |
| 文件大小： | 327K |
| 代理商： | M68AW127BM70NK1T |
M68AW127B
8/20
OPERATION
The M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 6).
Table 6. Operating Modes
Note: X = V
IH
or V
IL
.
Read Mode
The M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within t
AVQV
after the last stable address, provid-
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(t
ELQV
or t
GLQV
) rather than the address. Data out
may be indeterminate at t
ELQX
and t
GLQX
, but data
lines will always be valid at t
AVQV
.
Figure 8. Address Controlled, Read Mode AC Waveforms
Note: E1 = Low, E2 = High, G = Low, W = High.
Operation
E1
E2
W
G
DQ0-DQ7
Power
Read
V
IL
V
IH
V
IH
V
IH
Hi-Z
Active (I
CC
)
Read
V
IL
V
IH
V
IH
V
IL
Data Output
Active (I
CC
)
Write
V
IL
V
IH
V
IL
X
Data Input
Active (I
CC
)
Deselect
V
IH
X
X
X
Hi-Z
Standby (I
SB
)
Deselect
X
V
IL
X
X
Hi-Z
Standby (I
SB
)
AI05474
tAVAV
tAVQV
tAXQX
A0-A16
DQ0-DQ7
VALID
DATA VALID
相关PDF资料 |
PDF描述 |
|---|---|
| M68AW127BL10NK1T | Thick Film Resistor Network; Series:RNA4A; Resistance:10kohm; Resistance Tolerance:+/- 5 %; Power Rating:0.063W; Temperature Coefficient:+/-250 ppm; Package/Case:10-SOIC; Leaded Process Compatible:Yes; Mounting Type:Surface Mount |
| M68AW127BM10NK1T | Thick Film Resistor Network; Series:RNA4A; Resistance:100kohm; Resistance Tolerance:+/- 5 %; Power Rating:0.063W; Voltage Rating:25V; Temperature Coefficient:+/-250 ppm; Package/Case:10-SOIC; Network Circuit Type:Dual Termination |
| M68AW127BL70NK6T | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
| M68AW127BM70NK6T | 1Mbit 128K x8, 3.0V Asynchronous SRAM |
| M68AW127BL70MC1T | CAC 6C 6#16S SKT PLUG |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M68AW127BM70NK6 | 功能描述:静态随机存取存储器 1 MBIT (128K X8)静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| M68AW127BM70NK6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM |
| M68AW127BMC | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM |
| M68AW127BN | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM |
| M68AW127BNK | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1Mbit 128K x8, 3.0V Asynchronous SRAM |
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