参数资料
型号: M74HC173M1R
厂商: 意法半导体
元件分类: 通用总线功能
英文描述: QUAD D-TYPE REGISTER 3-STATE
中文描述: 四D型寄存器三态
文件页数: 1/12页
文件大小: 262K
代理商: M74HC173M1R
M54HC173
M74HC173
October 1992
QUAD D-TYPE REGISTER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HC173F1R
M74HC173B1R
M74HC173M1R
M74HC173C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
DESCRIPTION
TheM54/74HC173is ahigh speedCMOSQUADD-
TYPE REGISTER (3-STATE) fabricated in silicon
gate C
2
MOS technology.
It has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
Thisdevice iscomposed ofa four-bit registerinclud-
ingD-typeflip-flopsand3-statebuffers. Thefourflip-
flops are controlled by a common clock input
(CLOCK) and a common reset input (CLEAR). Sig-
nals applied to the data inputs (D
1
-D
4
) arestored at
the respective flip-flops on the positive going transi-
tion of the clock input, only when both clock control
inputs (G
1
and G
2
) are held low.
The reset feature is asynchronous and active high.
The stored data are provided on each output only
when both output control inputs (M and N) are held
low,otherwise theoutputs gotothehigh-impedance
state.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
.
HIGH SPEED
f
MAX
= 73 MHz (TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) at T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS 173
1/12
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