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参数资料
| 型号： | M74HC646RM13TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 总线收发器 |
| 英文描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封装： | SOP-24 |
| 文件页数： | 8/15页 |
| 文件大小： | 514K |
| 代理商： | M74HC646RM13TR |
M74HC646
2/15
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK AB
(CAB)
A to B Clock Input (LOW
to HIGH, Edge-Triggered)
2
SELECT AB
(SAB)
Select A to B Source Input
3
DIR
Direction Control Input
4, 5, 6, 7, 8,
9, 10, 11
A1 to A8
A Data Inputs/Outputs
20, 19, 18,
17, 16, 15,
14, 13
B1 to B8
B Data Inputs/Outputs
21
G
Output Enable Input
(Active LOW)
22
SELECT BA
(SBA)
Select B to A Source Input
23
CLOCK BA
(CBA)
B to A Clock Input (LOW
to HIGH, Edge Triggered)
12
GND
Ground (0V)
24
VCC
Positive Supply Voltage
G
DIR CAB CBA SAB SBA
A
B
FUNCTION
HX
INPUTS
Both the A bus and the B bus are inputs
X
Z
The Output functions of the A and B bus are disabled
X
INPUTS
Both the A and B bus are used for inputs to the internal
flip-flops. Data at the bus will be stored on low to high
transition of the clock inputs.
LH
INPUTS
OUTPUTS The A bus are inputs and the B bus are outputs
XX*
L
X
LL
The data at the A bus are displayed at the B bus
HH
X*
L
X
L
The data at the A bus are displayed at the B bus. The
data of the A bus are stored to internal flip-flop on low
to high transition of the clock pulse
HH
XX*H
X
Qn
The data stored to the internal flip-flop are displayed at
the B bus.
X*
H
X
L
The data at the A bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the B bus.
HH
LL
OUTPUTS
INPUTS
The B bus are inputs and the A bus are outputs.
X*
X
L
LL
The data at the B bus are displayed at the A bus
HH
X*
X
L
The data at the B bus are displayed at the A bus. The
data of the B bus are stored to the internal flip-flop on
low to high transition of the clock pulse.
HH
X*
X
H
Qn
X
The data stored to the internal flip-flops are displayed
at the A bus
X*
X
H
L
The data at the B bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the A bus.
HH
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