参数资料
型号: M87C257-20XF6TR
厂商: 意法半导体
元件分类: DRAM
英文描述: ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM
中文描述: 地址锁存256K 32K的× 8紫外线EPROM和检察官办公室存储器
文件页数: 4/13页
文件大小: 143K
代理商: M87C257-20XF6TR
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveform
AI01823
1.3V
OUT
CL = 30pF or 100pF
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table 5. AC Measurement Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note:
1. Sampled only, not 100% tested.
Table 6. Capacitance
(1)
(T
A
= 25
°
C, f = 1 MHz )
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can
be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1
μ
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
μ
F bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
4/13
M87C257
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