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参数资料
| 型号： | M8803F2Y-90T1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 16/85页 |
| 文件大小： | 601K |
| 代理商： | M8803F2Y-90T1 |
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M88 FAMILY
t EEPROM Sectors EES0-1 will be mapped in the
Program Space from 0000h-3FFFh. EEPROM
Sectors EES2-3 will be mapped in the Data Space
from 0000h-3FFFh. Bits 1 and 3 of the VM
Register are set to 1.
t SRAM will be mapped in the Data Space from
4000h-47FFh. Bit 0 of the VM Register is set to 0.
The Abel equations in PSDsoft will be as followed
(assumes active-low RD signal):
FS0 = (Address>= ^h8000) & (Address<=^hBFFF );
FS1 = (Address>= ^hC000) & (Address<=^hFFFF );
EES0 = (Address>= ^h0000) & (Address<=^h1FFF ) & RD;
EES1 = (Address>= ^h2000) & (Address<=^h3FFF ) & RD;
EES2 = (Address>= ^h0000) & (Address<=^h1FFF ) & !RD;
EES3 = (Address>= ^h2000) & (Address<=^h3FFF ) & !RD;
RS0 = (Address>= ^h4000) & (Address<=^h47FF);
When the microcontroller reads the VM register,
the contents read back are shown in Table 16. The
VM Register content at power up is specified in
PSDsoft.
Page Register
The eight bit Page
Register increases the
addressing capability of the microcontroller by a
factor of up to 256. The contents of the register
can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR7) are
inputs to the DPLD decoder and can be included
in the Flash Memory, EEPROM, and SRAM chip
select equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 13 shows the Page Register. The eight flip
flops in the register are connected to the internal
data bus D0-D7. The microcontroller can write to
or read from the Page Register. The Page
Register can be accessed at address location
CSIOP + E0h.
PLDs
The PLDs bring programmable logic functionality
to the M88x3Fxx FLASH+PSD. After specifying
the logic for the PLDs using the PSDabel tool in
PSDsoft, the logic is programmed into the device
and available upon power-up.
The M88x3Fxx FLASH+PSD contains two PLDs:
the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLDs are briefly discussed in the
next few paragraphs, and in more detail in the
section entitled “Decode PLD (DPLD)”, on page
25, and the section entitled “Complex PLD
(CPLD)”, also on page 25. Figure 14 shows the
configuration of the PLDs.
The DPLD performs address decoding for internal
and external components, such as memory,
registers, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable
counters
and
shift registers,
state
machines, and encoding and decoding logic.
These logic functions can be constructed using the
16
Output
Macrocells
(OMCs),
24
Input
Macrocells (IMCs), and the AND array. The CPLD
can also be used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 17.
The Turbo Bit in M88x3Fxx FLASH+PSD
The PLDs in the M88 Family can minimize power
consumption by switching off when inputs remain
Table 16. VM Register Contents in the 80C31 Memory Map Example
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RD_EN
Bit 0
PSEN_EN
0 = disable
PIO mode
not used
1= RD
can
access
Flash
1= RD
can
access
EEPROM/
Boot Flash
1 = PSEN
can
access
Flash
1 = PSEN
can
access
EEPROM/
Boot Flash
0 = PSEN
cannot
access
SRAM
Figu re 10. 80C31 Memory Map Example
Flash
Memory
Sectors
FS0-1
Program Space
EEPROM
Sectors
EES0-1
FFFFH
8000H
4000H
0
Flash
Memory
Sectors
FS0-1
Data Space
SRAM
EEPROM
Sectors
EES2-3
FFFFH
8000H
47FFH
4000H
0
AI02868
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相关代理商/技术参数 |
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| M8805/100-007 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-007 |
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| M8805/100-010 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-010 |
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