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| 型号： | M901-01I690.5692 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 690.5692 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 3/8页 |
| 文件大小： | 334K |
| 代理商： | M901-01I690.5692 |
M901-01 Datasheet Rev 4.0
3 of 8
Revised 30Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M901-01
VCSO BASED CLOCK GENERATOR
Prod uct Data Sh eet
FUNCTIONAL DESCRIPTION
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to an input reference clock. The M901-01
combines the flexibility of a VCSO (Voltage Controlled
SAW Oscillator) with the stability of a crystal oscillator.
The M901-01 uses a high-Q, narrow tuning range
VCSO with a center frequency that is specified at time
of device order (see Ordering Information on pg. 8).
A suitable reference clock frequency, M Divider setting,
and loop filter configuration must be used to assure
proper operation.
Input Reference
An input clock reference is required. It should be a
stable external clock source, such as a packaged
crystal oscillator or distributed system clock. The clock
reference is applied to the REF_IN input pin, which is
internally applied to the non-inverting input of the phase
detector.
Internal PLL Operation
The internal PLL is comprised of a first order, type 3
frequency/phase detector, a SAW delay-line based
VCO (VCSO), and a clock feedback divider.
The clock feedback divider (M Divider) divides the
VCSO frequency and drives the inverting input of the
phase detector, which is compared to the input
reference clock. The PLL is “locked” when the phase
detector inputs are aligned in frequency and phase; the
phase detector output controls the VCSO frequency to
achieve this, and the external loop filter provides
stability to this frequency (and phase) control system.
Hence, the VCSO frequency operates at “M” times the
input reference frequency, thus accomplishing
frequency translation. The external loop filter also acts
as a low pass filter that provides attenuation of clock
jitter on the reference input.
The relationship between the VCSO output frequency,
the M divider, and the input reference frequency is
defined as follows:
The product of M and the input frequency must be such
that it falls within the “lock” range of the VCSO.
P Divider and Outputs
The M901-01 provides one differential LVPECL output
pair: FOUT, nFOUT. By using the P divider, the output
frequency can be the VCSO center frequency (Fvcso)
or 1/2, 1/4, or 1/8 Fvcso.
The P1 and P0 pins select the value for the P divider.
See Table 4, Pin Selection of P Divider Using P1:0
Pins, on pg. 2.
When the P divider is included, the complete
relationship for the output frequency is defined as:
Configuration of M and P Dividers
The M and P dividers can be set by pin configuration
using the input pins M0, M2 - M5, P0, and P1. The data on
pins M5:2 and M0 and on pins P1:0 is passed directly to the
M and P dividers.
The divider configuration of the M901-01 is reset and
the outputs disabled when the input pin OUT_EN is set
HIGH. MR is set LOW for divider configuration to be
operational.
Fvcso
Fref_in
M
×
=
Fvcso
Fref_in
M
P
-----
×
=
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