参数资料
型号: M906-01-125.2500
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 125 MHz, OTHER CLOCK GENERATOR, CQCC36
封装: 9 X 9 MM, CERAMIC, LCC-36
文件页数: 3/6页
文件大小: 282K
代理商: M906-01-125.2500
M906-01 Datasheet Rev 1.3
3 of 6
Revised 06Jan2004
Integ r ated Circuit Systems , Inc. Comm unications Modules www.i cst. com ● tel (508) 852-5400
M906-01
VCSO BASED GBE CLOCK GENERATOR
Preliminar y In f o r m atio n
FUNCTIONAL DESCRIPTION
The M906-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M906-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal device or a stable external clock source such as
a packaged crystal oscillator:
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load capacitors are also
required.
If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M906-01 includes a
reference divider that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output. This creates an output
frequency that is a multiple of the reference frequency
(which is output from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
For the M906-01-156.2500 (see “Ordering Information” on pg. 6):
VCSO output frequency = 156.25MHz
Input reference frequency = 25MHz
M=25
R= 4
Therefore, for the M906-01-156.2500:
25
156.25MHz = 25MHz
4
The product of the input crystal frequency and
falls within the lock range of the VCSO.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M906-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Fvcso
Fxtal
M
R
-----
×
=
External Loop Filter Component Values
PLL
Bandwidth
Damping
Factor
R loop
C loop R post C post
500
Hz
2.1
1.5
k
4.00F 50k 3300pF
1.5
kHz
3.3
4.7
k
1.00F 50k 1500pF
6.4
kHz
4.4
20.0
k
0.10F 20k
470
pF
10.6
kHz 1
Note 1: Recommended for most applications
4.2
33.0
k
0.033F 20k
470
pF
----------
×
M
R
-----
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
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