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参数资料
| 型号： | M928-02-700.0000LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 2/6页 |
| 文件大小： | 296K |
| 代理商： | M928-02-700.0000LF |
M928-02 Datasheet Rev 0.4
2 of 6
Revised 30Jul2004
I n teg r at ed Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● te l (5 08 ) 8 5 2 - 54 00
M928-02
VCSO BASED CLOCK GENERATOR
Preliminar y In f o r m atio n
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 5.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12, 13
FOUT0, nFOUT0
Output
No internal terminator
Clock output pairs, differential LVPECL output
(622.08 MHz for the M928-02-622.0800)
15, 16
FOUT1, nFOUT1
17, 18
FOUT2, nFOUT2
20, 21
FOUT3, nFOUT3
22, 23
FOUT4, nFOUT4
24, 25
FOUT5, nFOUT5
29, 30
FOUT6, nFOUT6
31, 32
FOUT7, nFOUT7
27
XTAL_1 / REF_IN
Input
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
28
XTAL_2
Input
External crystal connection. Leave unconnected
when driving pin 27 with external clock reference.
34, 35, 36
DNC
Do Not Connect.
Internal nodes. Connection to these pins can
cause erratic device operation.
Table 2: Pin Descriptions
Phase Locked Loop (PLL)
M928-02
VC
nVC
nOP_OUT
OP_OUT
OP_IN
nOP_IN
FOUT2
nFOUT2
FOUT4
nFOUT4
FOUT3
nFOUT3
FOUT6
nFOUT6
FOUT5
nFOUT5
FOUT7
nFOUT7
XTAL
OSC
FOUT0
nFOUT0
FOUT1
nFOUT1
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