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参数资料
| 型号： | M928-02I300.0000LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 300 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 1/6页 |
| 文件大小： | 296K |
| 代理商： | M928-02I300.0000LF |
M928-02 Datasheet Rev 0.4
Revised 30Jul2004
Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-5 400
M928-02
VCSO BASED CLOCK GENERATOR
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M928-02 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. From the
M928-02-622.0800
, an output clock
frequency of 622.08MHz is
provided from eight LVPECL clock
output pairs. (Other frequencies are available; consult
factory.) The accuracy of the output frequency is
assured by the internal PLL that phase-locks the
internal VCSO to the reference input frequency
(19.44MHz for the M928-02-622.0800). The input reference
can either be an external crystal, utilizing the internal
crystal oscillator, or a stable external clock source
such as a packaged crystal oscillator.
FEATURES
◆ Output clock frequency range 300MHz to 700MHz
(Consult factory for frequency availability)
◆ Eight identical LVPECL output pairs
◆ Jitter 0.7ps rms (@622.08MHz, over 12kHz-20MHz), typ.
◆ Ideal for OC-48/STM-16 clock reference
◆ Output-to-output skew < 100ps
◆ External XTAL or LVCMOS reference input
◆ Integrated SAW (surface acoustic wave) delay line
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Output Frequency Configurations
(M928-02-622.0800)
Ref Clock
Frequency
(MHz)
PLL
Multiplication
Ratio
VCSO and
Output
Frequency
(MHz)
Application
19.44
32
622.08
OC-48/STM-16
N
nOP
M928-02-622.08 (Other Frequencies Available)
External Loop Filter
M928-02 VCSO Based Clock Generator
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