- 您现在的位置：买卖IC网 > PDF目录359112 > M93S56-WBN6TP (意法半导体) 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection PDF资料下载
参数资料
| 型号： | M93S56-WBN6TP |
| 厂商： | 意法半导体 |
| 元件分类： | DRAM |
| 英文描述： | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| 中文描述： | 4Kbit，2Kbit和1Kbit 16位宽MICROWIRE串行EEPROM的访问与街区保护 |
| 文件页数： | 15/34页 |
| 文件大小： | 525K |
| 代理商： | M93S56-WBN6TP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
15/34
M93S66, M93S56, M93S46
ing the Protection Register Write (PRWRITE) in-
struction. When the OTP bit is set, the Ready/Busy
status cannot appear on Serial Data Output (Q).
When the OTP bit is not set, the Busy status ap-
pears on Serial Data Output (Q).
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Disable (PRDS) instruction.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note
AN394
for details.
Figure 8. Write Sequence with One Clock Glitch
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the Bus Master (the micro-
controller). This can lead to a misalignment of the
instruction of one or more bits (as shown in
Figure
8.
) and may lead to the writing of erroneous data
at an erroneous address.
To combat this problem, the M93Sx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, PAWRITE,
WRALL, PRWRITE or PRCLEAR instruction is
aborted, and the contents of the memory are not
modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Sx6
family, are summarized in
Table 2.
to
Table 3.
. For
example, a Write Data to Memory (WRITE) in-
struction on the M93S56 (or M93S66) expects 27
clock cycles from the start bit to the falling edge of
Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
AI01395
S
An-1
C
D
WRITE
START
D0
"1"
"0"
An
Glitch
An-2
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
相关PDF资料 |
PDF描述 |
|---|---|
| M93S56-WBN6TG | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WBN6T | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WBN6P | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WBN6G | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WBN6 | 4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M93S56-WDS3 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WDS3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WDS3P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WDS3T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
| M93S56-WDS3TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection |
发布紧急采购，3分钟左右您将得到回复。