参数资料
型号: M95020-RDW3TP/W
厂商: STMICROELECTRONICS
元件分类: PROM
英文描述: 256 X 8 SPI BUS SERIAL EEPROM, PDSO8
封装: 0.169 INCH, ROHS COMPLIANT, TSSOP-8
文件页数: 6/42页
文件大小: 250K
代理商: M95020-RDW3TP/W
Operating features
M95040, M95020, M95010
4.3
Data Protection and Protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
The WEL bit is reset at power-up.
Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status Register).
Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the "next rising edge of CLOCK" might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 3.
Write-Protected block size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95040
M95020
M95010
0
none
0
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
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