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参数资料
| 型号： | M95160-DW6 |
| 厂商： | 意法半导体 |
| 元件分类： | EEPROM |
| 英文描述： | 16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 16Kbit和8Kbit SPI总线串行EEPROM的高速时钟 |
| 文件页数： | 15/40页 |
| 文件大小： | 648K |
| 代理商： | M95160-DW6 |
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15/40
M95160, M95080
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in
Figure 10.
.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is t
W
) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in
Table 3.
.
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
Table 6. Protection Modes
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
Table 6.
.
The protection features of the device are summa-
rized in
Table 4.
.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
–
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is
not
possible to write to the Status Register
even
if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
–
W
Signal
SRWD
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area
1
Unprotected Area
1
1
0
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the BP1 and
BP0 bits can be changed
Write Protected
Ready to accept Write
instructions
0
0
1
1
0
1
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1 and
BP0 bits cannot be
changed
Write Protected
Ready to accept Write
instructions
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M95160-DW6G/G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-DW6G/S | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-DW6P/G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-DW6P/S | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock |
| M95160-DW6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
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