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参数资料
| 型号： | M95160-RBN3T |
| 厂商： | 意法半导体 |
| 元件分类： | EEPROM |
| 英文描述： | 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| 中文描述： | 64/32/16/8千位串行SPI总线的EEPROM高速时钟 |
| 文件页数： | 18/40页 |
| 文件大小： | 648K |
| 代理商： | M95160-RBN3T |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
M95160, M95080
18/40
Write to Memory Array (WRITE)
As shown in
Figure 12.
, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of
Figure 12.
, this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period t
WC
(as specified in
Ta-
ble 19.
to
Table 23.
), at the end of which the Write
in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in
Figure 13.
, the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
if a Write cycle is already in progress
–
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
–
if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) Sequence
Note: Depending on the memory size, as shown in
Table 7.
, the most significant address bits are Don’t Care.
C
D
AI01795D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
High Impedance
Instruction
16-Bit Address
0
7
6
5
4
3
2
0
1
Data Byte
31
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相关代理商/技术参数 |
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|---|---|
| M95160-RBN5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160-RBN6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95160RCS6TG/G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16-Kbit serial SPI bus EEPROM with high-speed clock |
| M95160RCS6TG/S | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16-Kbit serial SPI bus EEPROM with high-speed clock |
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