参数资料
型号: MA17502
厂商: Dynex Semiconductor Ltd.
英文描述: Radiation Hard MIL-STD-1750A Control Unit
中文描述: 辐射硬的MIL - STD - 1750A控制单元
文件页数: 8/30页
文件大小: 272K
代理商: MA17502
MA17502
8/30
MAS281
Instruction Counter (IC)
Status Word (EU and MMU) (SW)
Fault (FT)
Pending Interrupt (Pl)
Mask (MK)
General Register File (RO R15)
Interrupts
DMA Access
TimerA
Timer B
Trigger-Go Timer
Zeroed
Zeroed
Zeroed
Zeroed
Zeroed
Zeroed
Disabled
Disabled
Reset and Started
Reset and Started
Reset and Started
MMU
Page Registers
AL, W, E, Fields
PPA Field
Group Zero Enabled
Zeroed
Logical to Physical
Map
BPU
Write Protect
Global Memory Protect
Zeroed
Enabled
BIT
Test
Coverage
BIT Fail Codes
(FT
13, 14,15
)
Cycles
Microcode Sequencer
IB Register Control
Barrel Shifter
Byte Operations and
Flags
1
100
221
Temporary Registers
(T0 - T7)
Microcode Flags
Multiply
Divide
2
101
166
Interrupt Unit
MK, Pl, FT
Enable/Disable
Interrupts
3
111
214
Status Word Control
User Flags
General Registers
(R0 - R15)
4
110
154
5
Timer A
Timer B
111
763
BIT Pass/Fail
Overhead
-
26
Note:
BIT pass is indicated by all zeros in FT bits 13, 14 and 15
Table 3: Initialisation State
Table 4: Built In Test (BIT) Summary
driven low during execution of this instruction). Interrupt, DMA,
and Hold support are explained in more detail in following
sections.
4.3 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is controlled by the Execution
Unit (EU) in concert with the Interrupt Unit DMA interface. The
CU supports DMA by suspending processor control upon
completion of the current machine cycle. If DMA is enabled
((UI)DMAE signal, high) a DMA request ((IU)DMARN input,
low) to the MAS281 causes the lU to acknowledge with
DMAKN, low. When the EU receives the DMAKN (DMA
Acknowledge) signal from the lU, the CU clocks are suspended
(CLKPCN, low; CLK02N, high) halting the MAS281’s
microcode sequencing. Microinstruction execution remains
suspended until DMARN is removed. When DMARN is
removed, microcode execution resumes where DMARN had
interrupted it.
4.4 INTERRUPT HANDLING
Interrupts are handled by the interrupt Unit (IU) and
communicated to the CU via the lRN input. The CU checks the
status of the lRN (lnterrupt Request) signal after the completion
of each MlL-STD-1750A microcode instruction sequence. lf the
lRN signal is low, the CU initiates interrupt handling, otherwise
the CU processes a new instruction.
4.2 INSTRUCTION EXECUTION
The MIL-STD-1750A microcoded instruction subroutines
are stored in 1255 locations of microcode storage ROM. The
Control Unit receives instructions from memory, via the AD
Bus, through the instruction pipeline registers lA and IB. When
the previous instruction or special process (Interrupts or Hold)
has been completed, the new instruction residing in register IB
is selected by the next microcode address source multiplexer.
A 4-bit hardwired constant, appended by the instruction
opcode, is then used as the first address of a microcode
sequence which distributes the required control to execute the
instruction. The microsequencer generates the remaining
microcode addresses necessary to complete the sequence as
described in Section 2.0 of this data sheet entitled,
“Architecture”.
Upon completion of the current instruction, the CU will
accept the next instruction in the program unless an interrupt,
DMA, or Hold request is received. The interrupt and Hold
request share a common branch point in microcode. If an
interrupt and Hold request are both pending at the conclusion of
the MIL-STD-1750A instruction microcode routine, the Hold
request has priority and is serviced first. Upon release of the
Hold state, the first instruction will execute even if the interrupt
is still pending; when this instruction is complete the interrupt
will be serviced (assuming the HOLDN input has not been
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