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| 型号： | MA17503 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Radiation Hard MIL-STD-1750A Interrupt Unit |
| 中文描述： | 辐射硬的MIL - STD - 1750A中断组 |
| 文件页数： | 11/34页 |
| 文件大小： | 373K |
| 代理商： | MA17503 |
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MA17503
11/34
Each of the nine user interrupt inputs is buffered by a falling-
edge detector to prevent repeat latching of requests held low
longer than the first SYNCLKN high-to-low transition. An
interrupt request input must go back to the high state before
request on that input can be detected.
Command
M04, M05, M06
Load Fault Register From AD Bus
001
Read Interrupt Priority Vector
Onto AD Bus
010
Raise Normal Power-up Discrete
011
Disable l/O Control of DMA lnterface
100
Enable l/O Control of DMA Interface
101
The output of the Pl register is continually ANDed with the
output of the MK register (level 0 interrupt is not maskable). If
interrupts are enabled, and an unmasked interrupt is pending,
the Interrupt Request (IRN) output to the Control Unit is
asserted. This occurs when one or more interrupts are latched
and unmasked. The unmasked pending interrupts are output to
the priority encoder where the highest priority pending interrupt
is encoded as a 4-bit vector.
After the currently executing MIL-STD-1750A instruction is
completed, the Control Unit checks the state of the lRN input. If
IRN is asserted, a branch is made to the microcode interrupt
service routine. During this routine, the priority encoder's 4-bit
vector is read into the Execution Unit, where the vector is used
to calculate the appropriate interrupt linkage and service
pointers (Table 6). When the EU reads the interrupt priority
vector from the lU, the interrupt being serviced is cleared from
the Pl. If no other interrupts are pending, this also causes the
IRN signal to be deactivated.
4.4 FAULT SERVICING
Eight external fault inputs are provided to the interrupt unit.
A low on any of these inputs is latched into the FT register at the
high-to-low transition of SYNCLKN. The capture of one or more
of these faults immediately sets pending interrupt level 1
(machine error) of the Pl.
Anti-repeat logic between the FT and Pl prevents latching
more than a single interrupt into the Pl before the user interrupt
service routine has cleared the FT. The microcoded interrupt
service routine reads the interrupt priority vector from the
Interrupt Unit and clears the serviced interrupt from the Pl. At
this point the Pl is ready to latch another interrupt into this bit.
When this microcoded service routine acts on a level 1
interrupt, it clears the Pl bit 1, but the FT maintains the
interrupting fault bit(s). Therefore, a level 1 interrupt would be
latched again if there was no anti-repeat logic to prevent a
never ending loop of interrupts from occurring.
Interrupts are serviced at the end of the currently executing
instruction if not masked and if interrupts are enabled. System
software servicing level 1 interrupts must clear the FT via the
RCFR internal l/O command at some point in the routine to
allow subsequent faults to latch a level 1 interrupt request. A
non-destructive read of the FT is provided by the internal I/O
command RFR, but this command should be used carefully.
Faults caused by a low on EXADEN, MPROEN, or Bus
Fault Timer expiration (FT 0, 5, 8) require that the currently
executing MlL-STD-1750A instruction be aborted. In order to
accomplish this, the latching of faults 0, 5, or 8 causes the
lnterrupt Unit to assert the instruction abort (PIFN) output to
both the Execution Unit and the Control Unit Faults 0, 5, and 8
are not latched during DMA cycles or the Hold state (CDN low).
Table 5: Interrupt Unit Microcode Commands
Interrupt
Number
Priority
(1)
Level
Linkage
Pointer
Service
Pointer
Functlon
Maskable
Dlsablllty
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Power Down
Machine Error
User 0
Floating Point Overflow
Fixed Point Overflow
Executive Call
Floating Point Underflow
Timer A
User 1
Timer B
User 2
User 3
l/O 1
User 4
I/O 2
User 5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
21
23
25
27
29
2B
2D
2F
31
33
35
37
39
3B
3D
3F
Note:
(1) Level 0 has highest priority, level 15 lowest.
Table 6: Interrupt Vector Assignments
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