2011 Microchip Technology Inc.
DS39932D-page 11
PIC18F46J11 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
1.1
Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F46J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key features are:
Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operational requirements.
On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the users to incorporate
power-saving ideas into their application’s
software design.
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F46J11 family offer five
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
Two Crystal modes using crystals or ceramic
resonators.
Two External Clock modes offering the option of a
divide-by-4 clock output.
An internal oscillator block, which provides an
8 MHz clock and an INTRC source (approxi-
mately 31 kHz, stable over temperature and VDD),
as well as a range of six user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees
an oscillator pin for use as an additional general
purpose I/O.
A Phase Lock Loop (PLL) frequency multiplier,
available to the high-speed crystal, and external
and internal oscillators, providing a clock speed
up to 48 MHz.
The internal oscillator block provides a stable reference
source that gives the PIC18F46J11 family additional
features for robust operation:
Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset (POR), or wake-up from
Sleep mode, until the primary clock source is
available.
1.1.3
EXPANDED MEMORY
The PIC18F46J11 family provides ample room for
application code, from 16 Kbytes to 64 Kbytes of code
space. The Flash cells for program memory are rated
to last in excess of 10000 erase/write cycles. Data
retention without refresh is conservatively estimated to
be greater than 20 years.
The Flash program memory is readable and writable
during normal operation. The PIC18F46J11 family also
provides plenty of room for dynamic application data
with up to 3.8 Kbytes of data RAM.
PIC18F24J11
PIC18LF24J11
PIC18F25J11
PIC18LF25J11
PIC18F26J11
PIC18LF26J11
PIC18F44J11
PIC18LF44J11
PIC18F45J11
PIC18LF45J11
PIC18F46J11
PIC18LF46J11