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参数资料
| 型号： | MA300012 |
| 厂商： | Microchip Technology |
| 文件页数： | 10/92页 |
| 文件大小： | 0K |
| 描述： | MODULE DSPIC30F SAMPLE 64QFP |
| 标准包装： | 1 |
| 模块/板类型： | dsPIC30F 插件模块 |
| 适用于相关产品： | DM240001 |
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dsPIC30F
5.0
CPU ARCHITECTURE
FIGURE 5-1:
PROGRAM SPACE
MEMORY MAP
5.1
Overview
Reset – GOTO Instruction
000000
The dsPIC30F CPU module has a 16-bit (data)
modified Harvard architecture with an enhanced
Reset – Target Address
Reserved
Osc. Fail Trap Vector
000002
000004
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word, with a variable
length opcode field. The Program Counter (PC) is 23
bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
varies from one device to another. A single-cycle
instruction pre-fetch mechanism is used to help
Address Error Trap Vector
Stack Error Trap Vector
Arithmetic Warn. Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt Vector Table
000014
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
Reserved
00007E
000080
000084
with the exception of instructions that change the
program flow, the double-word move ( MOV.D )
instruction and the table instructions. Overhead free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
Alternate Vector Table
User Flash
Program Memory
(48K instructions)
0000FE
000100
The dsPIC30F devices have sixteen 16-bit working
registers in the programmer’s model. Each of the
working registers can serve as a data, address or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer for
interrupts and calls.
The dsPIC30F instruction set has two classes of
Reserved
(Read 0’s)
Data EEPROM
(4 Kbytes)
017FFE
018000
7FEFFE
7FF000
7FFFFE
800000
instructions: the MCU class of instructions and the DSP
class of instructions. These two instruction classes are
seamlessly integrated into the architecture and
execute from a single execution unit. The instruction
set includes many addressing modes and is designed
for optimum C compiler efficiency.
Reserved
5.1.1
DATA MEMORY OVERVIEW
The data space can be addressed as 32 Kwords or 64
Kbytes and is split into two blocks, referred to as X and
Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Device Configuration
Registers
Reserved
F7FFFE
F80000
F8000E
F80010
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
FFFFFE
DS70043F-page 8
? 2005 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MA300013 | 功能描述:子卡和OEM板 dsPIC30F 80L Plug In Sample RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA300013 | 制造商:Microchip Technology Inc 功能描述:Tools Development kit Kit Con |
| MA300014 | 功能描述:子卡和OEM板 dsPIC30F 80L Plug In Sample (6014A) RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA300015 | 功能描述:子卡和OEM板 dsPIC30F 80L Plug In Sample (6010A). RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| MA300016 | 功能描述:子卡和OEM板 dsPICDEM 80-PIN PIM RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
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