参数资料
型号: MAC7121MAG40
厂商: Freescale Semiconductor
文件页数: 9/56页
文件大小: 0K
描述: IC MCU 32BIT FLASH 112-LQFP
标准包装: 60
系列: MAC7xxx
核心处理器: ARM7
芯体尺寸: 32-位
速度: 40MHz
连通性: CAN,I²C,SCI,SPI
外围设备: DMA,POR
输入/输出数: 85
程序存储器容量: 544KB(544K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.35 V ~ 5.5 V
数据转换器: A/D 16x8/10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 112-LQFP
包装: 托盘
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
17
The capacitance CP should be chosen in the range of:
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1
Jitter Information
With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
Figure 4. Jitter Definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for
larger number of clock periods (N). Thus, jitter is defined as:
Eqn. 15
For N
< 100, the following equation is a good fit for the maximum jitter:
Eqn. 16
Figure 5. Maximum Bus Clock Jitter Approximation
C
S
20
÷
C
P
C
S
10
÷
≤≤
0
tMIN1
12
3
N–1
N
tNOM
tMAX1
tMIN(N)
tMAX(N)
JN
()
max 1
t
MAX N
()
Nt
NOM
--------------------
–1
t
MIN N
()
Nt
NOM
--------------------
,
=
JN
()
j
1
N
--------
j
2
+
=
01
5
10
20
15
N
J(N)
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