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参数资料
| 型号： | MACH211SP-10VC |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High-Performance EE CMOS In-System Programmable Logic |
| 中文描述： | 高性能电子工程的CMOS在系统可编程逻辑 |
| 文件页数： | 28/37页 |
| 文件大小： | 251K |
| 代理商： | MACH211SP-10VC |
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28
MACH211SP-7/10/12/15/20
F
MAX
PARAMETERS
The parameter f
MAX
is the maximum clock rate at which
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f
MAX
is specified for
three types of synchronous designs.
The first type of design is a state machine with feed-
back signals sent off-chip. This external feedback could
go back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the
input setup time for the external signals (t
S
+ t
CO
). The
reciprocal, f
MAX
, is the maximum frequency with exter-
nal feedback or in conjunction with an equivalent speed
device. This f
MAX
is designated “f
MAX
external.”
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by
the internal delay from the flip-flop outputs through the
internal feedback and logic to the flip-flop inputs. This
f
MAX
is designated “f
MAX
internal”. A simple internal
counter is a good example of this type of design; there-
fore, this parameter is sometimes called “f
CNT.
”
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
S
+ t
H
). How-
ever, a lower limit for the period of each f
MAX
type is the
minimum clock period (t
WH
+ t
WL
). Usually, this mini-
mum clock period determines the period for the third
f
MAX
, designated “f
MAX
no feedback.”
For devices with input registers, one additional f
MAX
pa-
rameter is specified: f
MAXIR
. Because this involves no
feedback, it is calculated the same way as f
MAX
no
feedback. The minimum period will be limited either by
the sum of the setup and hold times (t
SIR
+ t
HIR
) or the
sum of the clock widths (t
WICL
+ t
WICH
). The clock
widths are normally the limiting parameters, so that
f
MAXIR
is specified as 1/(t
WICL
+ t
WICH
). Note that if both
input and output registers are use in the same path, the
overall frequency will be limited by t
ICS
.
All frequencies except f
MAX
internal are calculated from
other measured AC parameters. f
MAX
internal is mea-
sured directly.
t
SIR
CLK
LOGIC
REGISTER
CLK
LOGIC
REGISTER
t
S
CLK
LOGIC
REGISTER
f
MAX
External; 1/(t
S
+ t
CO
)
f
MAX
Internal (f
CNT
)
f
MAX
No Feedback; 1/(t
S
+ t
H
) or 1/(t
WH
+ t
WL
)
f
MAXIR
; 1/(t
SIR
+ t
HIR
) or 1/(t
WICL
+ t
WICH
)
t
S
t
CO
t
S
CLK
LOGIC
REGISTER
(SECOND
CHIP)
t
HIR
20405B-21
相关PDF资料 |
PDF描述 |
|---|---|
| MACH211SP-12 | High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-12JC | High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-12VC | High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-14 | High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-15 | High-Performance EE CMOS In-System Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH211SP-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-12JC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High-Performance EE CMOS In-System Programmable Logic |
| MACH211SP-12JI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH211SP-12VC | 制造商:Lattice Semiconductor Corporation 功能描述: |
| MACH211SP-14 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High-Performance EE CMOS In-System Programmable Logic |
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