- 您现在的位置：买卖IC网 > PDF目录365230 > MACH220-15 (ADVANCED MICRO DEVICES INC) High-Density EE CMOS Programmable Logic PDF资料下载
参数资料
| 型号： | MACH220-15 |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, PQCC68 |
| 文件页数： | 12/33页 |
| 文件大小： | 230K |
| 代理商： | MACH220-15 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
AMD
12
MACH220-12/15/20 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
C
IN
C
OUT
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2.0 V
V
OUT
= 2.0 V
Typ
6
8
Unit
pF
pF
V
CC
= 5.0 V, T
A
= 25
°
C,
f = 1 MHz
SWITCHING CHARACTERISTICS over
COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
Min
Max
Min
Max
Min
Max
Unit
t
PD
Input, I/O, or Feedback to Combinatorial Output (Note 3)
12
15
20
ns
7
10
13
ns
8
11
14
ns
t
H
Register Data Hold Time
0
0
0
ns
t
CO
Clock to Output (Note 3)
8
10
12
ns
t
WL
Clock Width
6
6
8
ns
t
WH
6
6
8
ns
66.7
50
40
MHz
62.5
47.6
38.5
MHz
f
MAX
Frequency
(Note 1)
83.3
66.6
50
MHz
76.9
62.5
47.6
MHz
83.3
83.3
62.5
MHz
t
SL
Setup Time from Input, I/O, or Feedback to Gate
7
10
13
ns
t
HL
Latch Data Hold Time
0
0
0
ns
t
GO
Gate to Output (Note 3)
10
11
12
ns
t
GWL
Gate Width LOW
6
6
8
ns
t
PDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
14
17
22
ns
t
SIR
Input Register Setup Time
2
2
2
ns
t
HIR
Input Register Hold Time
2
2.5
3
ns
t
ICO
Input Register Clock to Combinatorial Output
15
18
23
ns
t
ICS
Input Register Clock to Output Register Setup
12
15
20
ns
13
16
21
ns
t
WICL
6
6
8
ns
t
WICH
6
6
8
ns
f
MAXIR
Maximum Input Register Frequency 1/(t
WICL
+ t
WICH
)
83.3
83.3
62.5
MHz
t
SIL
Input Latch Setup Time
2
2
2
ns
t
HIL
Input Latch Hold Time
2
2.5
3
ns
t
IGO
Input Latch Gate to Combinatorial Output
17
20
25
ns
t
IGOL
Input Latch Gate to Output Through Transparent
Output Latch
19
22
27
ns
t
SLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
9
12
15
ns
t
IGS
Input Latch Gate to Output Latch Setup
13
16
21
ns
-15
-12
-20
Maximum
t
S
Setup Time from Input, I/O, or Feedback to Clock
1/(t
S
+ t
CO
)
Internal Feedback (f
CNT
)
No Feedback 1/(t
WL
+ t
WH
)
External Feedback
D-type
T-type
D-type
T-type
D-type
T-type
D-type
T-type
LOW
HIGH
LOW
HIGH
Input Register Clock Width
相关PDF资料 |
PDF描述 |
|---|---|
| MACH220-15JI | High-Density EE CMOS Programmable Logic |
| MACH220-20 | High-Density EE CMOS Programmable Logic |
| MACH220-20JI | High-Density EE CMOS Programmable Logic |
| MAX542 | Quadruple Bus Buffer Gate With 3-State Outputs 14-PDIP -40 to 85 |
| MAX542ACPD | +5V, Serial-Input, Voltage-Output, 16-Bit DACs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH220-15JC | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH220-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:Electronic Component |
| MACH220-15JI | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH220-20 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH220-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。