参数资料
型号: MACHLV210-12JC
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
英文描述: High Density EE CMOS Programmable Logic
中文描述: EE PLD, 12 ns, PQCC44
封装: PLASTIC, LCC-44
文件页数: 17/29页
文件大小: 221K
代理商: MACHLV210-12JC
17
MACHLV210-18/24 (Ind)
SWITCHING CHARACTERISTICS over
INDUSTRIAL operating ranges (Note 2)
(continued)
Parameter
Symbol
t
WIGL
t
PDLL
Parameter Description
Input Latch Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 3)
Input, I/O, or Feedback to Output Disable (Note 3)
Min
6
Max
Min
8.5
Max
Unit
ns
ns
25.5
34
t
AR
t
ARW
t
ARR
t
AP
t
APW
t
APR
t
EA
t
ER
24
31.5
ns
ns
ns
ns
ns
ns
ns
ns
18
18
24
24
24
31.5
18
18
24
24
18
18
24
24
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit at the back of this Data
Sheet
for test conditions.
3. Parameters measured with 16 outputs switching.
-18
-24
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