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参数资料
型号： MAS3509F
厂商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分类： Codec
英文描述： MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
中文描述： 新加坡金融管理局35x9F的MPEG 2 / 3层，AAC音频解码器，G.729的附件A编解码器
文件页数： 21/92页
文件大小： 1186K
代理商： MAS3509F
DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
21
2.11.4.Control of the Signal Processing
Before starting the DSP, the controller should check
for a sufficient voltage supply (respective flag PUPn at
I
2
C subaddress 76
hex
). The DSP is enabled by setting
the appropriate bit in the Control register (I
2
C subad-
dress 6A
hex
). The nominal frequency of the crystal
oscillator must be written into D0:348. After an initial-
ization phase of 5 ms, the DSP data registers can be
accessed via I
2
C.
Input and output control is performed via memory loca-
tion D0:346 and D0:347. The serial input interface
SDIB is the default. The decoded audio can be routed
to either the S/PDIF, the SDO and the analog outputs.
The output clock signal at pin CLKO is defined in
D0:349.
All changes in the D0 memory cells become effective
synchronously upon setting the LSB of Main I/O Con-
trol (see Table 3–8 on page 32). Therefore, this cell
should always be written last.
The digital volume control (see Table 3–8 on page 32)
is applied to the output signal of the DSP. The
decoded audio data will be available at the SPDO out-
put interface in the next version.
The DSP does not have to be started if its functions
are not required, e.g., for routing audio through the
codec part of the IC via the A/D and the D/A convert-
ers.
2.11.5.Start-up of the Audio Codec
Before enabling the audio codec, the controller should
check for a sufficient voltage supply (respective flag
PUPn at I
2
C subaddress 76
hex
).
The audio codec is enabled by setting the appropriate
bit at the Control register (I
2
C subaddress 6A
hex
). After
an initialization phase of 5 ms, the DSP data registers
can be accessed via I
2
C. The A/D and the D/A con-
verters must be switched on explicitly (register
00 00
hex
at I
2
C subaddress 6C
hex
). The D/A convert-
ers may either accept data from the A/D converters or
the output of the DSP, or a mix of both
1)
(register
00 06
hex
and 00 07
hex
at I
2
C subaddress 6C
hex
).
Finally, an appropriate output volume (register
00 10
hex
at I
2
C subaddress 6C
hex
) must be selected.
2.11.6.Power-Down
All analog outputs should be muted and the A/D and
the D/A converters must be switched off (register
00 10
hex
and 00 00
hex
at I
2
C subaddress 6C
hex
). The
DSP and the audio codec must be disabled (clear
DSP_EN and CODEC_EN bits in the Control register,
I
2
C subaddress 6A
hex
). By clearing both DC/DC
enable flags in the Control register (I
2
C subaddress
6A
hex
), the microcontroller can power down the com-
plete system.
1) mixer available in version A2 and later; in version
A1, please use selector 00 0F
hex
.
相关PDF资料
PDF描述
MAS3519F MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
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相关代理商/技术参数
参数描述
MAS3519F 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
MAS3529F 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
MAS3539F 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
MAS3549F 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
MAS3559F 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
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