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参数资料
| 型号： | MAS3587F |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | 通用总线功能 |
| 英文描述： | MPEG Layer 3 Audio Encoder/Decoder |
| 中文描述： | MPEG层3音频编码器/解码器 |
| 文件页数： | 32/83页 |
| 文件大小： | 734K |
| 代理商： | MAS3587F |
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MAS 3587F
ADVANCE INFORMATION
32
Micronas
3.3.2. List of DSP Registers
Table 3
–
5 lists the registers used in the standard firmware (MPEG) and for the download option (Download).
Note:
Registers not given in the tables must not be written.
Table 3
–
5:
DSP Register Table
3.3.3. List of DSP Memory Cells
Among the user interface control memory cells there
are some which have a global meaning and some
which control application specific parts of the DSP
core. In the tables below this is reflected by the key-
words All, Encoder and Decoder.
3.3.3.1. Application Select and Running
The AppSelect cell is a global user interface configura-
tion cell, which has to be written in order to start a spe-
cific application.
The AppRunning cell is a global user interface status
cell, which indicates, which application loop is actually
running.
The meaning of the bits in both cells is given in Table
3
–
6.
Following steps have to be performed to switch
between applications:
–
write
“
0
”
to AppSelect
–
check AppRunning for
“
0
”
–
apply necessary/wanted Control settings
–
write value to AppSelect according to Table 3
–
6
3.3.3.2. Application Specific Control
The configuration of the MPEG Encoder and Decoder
firmware is done via the control memory cells
described in Table 3
–
7. The changes applied to any of
the control memory cells have to be validated by set-
ting bit[0] of memory cell Main I/O Control except when
the application is started by writing the AppSelect
memory cell. The validate bit will be reset automati-
cally after the changes have been taken over by the
DSP.
The status memory cells are used to read the encoder/
decoder status and to get additional MPEG bitstream
information.
Note:
Memory cells not given in the tables must not be
written.
Address
(hex)
R/W
FunctionMode
Default
(hex)
Name
6B
R/W
Configuration of Variable RAM Areas
Download
Affected RAM area
D0:800 ... D0:BFF
D0:C00 ... D0:FFF
D1:800 ... D1:BFF
D1:C00 ... D1:FFF
bit[19]
bit[18]
bit[17]
bit[16]
This register is used to switch four RAM areas from data
to program usage and thus enabling the DSP
’
s program
counter to access downloaded program code stored at
these locations. For normal operation (firmware in ROM)
this register must be kept to zero.
For details of program code download please refer to
Section 3.3.1.14.
0000
PSelect_Shadow
56
R
S/PDIF
1)
Input Channel Status Bits
MPEG
bit[15:0]
channel status bits of incoming signal.
0000
SPIChannelStatus
1)
IEC 958 Amendment1,
“
Digital Audio Interface
”
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相关代理商/技术参数 |
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