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参数资料
| 型号： | MAX1003CAX+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC ADC 6BIT 90MSPS DL 36-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| 位数： | 6 |
| 采样率（每秒）： | 90M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 941mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-BSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.)
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCC supply voltage,
expressed in decibels.
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22F at Q and I compensation inputs (Figures 2 and 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, VCC
GAIN = open (mid gain), fIN = 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOBM
5.6
5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Q channel
I channel
dB
CONDITIONS
MHz
55
BW
Analog Input -0.5dB Bandwidth
Msps
90
fMAX
Maximum Sample Rate
-55
XTLK
GAIN = VCC (high gain)
Crosstalk Between ADCs
LSB
-0.5
0.5
OFF
Input Offset (Note 5)
-0.5
0.5
dB
35.5
37
SINAD
Signal-to-Noise plus Distortion
Ratio
Bits
5.85
ENOBL
5.8
ENOBH
(Note 5)
dB
-0.2
±0.1
0.2
AM
Amplitude Match Between
ADCs
LSB
-0.5
±0.25
0.5
OMM
Offset Mismatch Between ADCs
(Note 6)
ns
1.5
tSKEW
Data Valid Skew
ns
3.6
tPD
Clock to Data Propagation
Delay
degrees
-2
±0.5
2
PM
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6)
ns
5.3
tDCLK
Input to DCLK Delay
Figure 8
ns
7.5
tAD
Aperture Delay
Figure 8
clock
cycle
1
PD
Pipeline Delay
TIMING CHARACTERISTICS (Data outputs: RL = 1M, CL = 15pF)
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
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相关代理商/技术参数 |
参数描述 |
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| MAX1003EVKIT | 功能描述:数据转换 IC 开发工具 RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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| MAX1005CEE | 功能描述:射频无线杂项 RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005CEE+ | 功能描述:射频无线杂项 IF Undersampler RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005CEE+T | 功能描述:射频无线杂项 IF Undersampler RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
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