参数资料
型号: MAX1062CEUB+T
厂商: Maxim Integrated Products
文件页数: 2/18页
文件大小: 0K
描述: IC ADC 14BIT 200KSPS 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 14
采样率(每秒): 200k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 444mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-µMAX
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
MAX1062
Output Coding and
Transfer Function
The data output from the MAX1062 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1LSB = 250V or 4.096V/16384).
Applications Information
External Reference
The MAX1062 requires an external reference with a
voltage range between 3.8V and AVDD. Connect the
external reference directly to REF. Bypass REF to
AGND (pin 3) with a 4.7F capacitor. When not using a
low ESR bypass capacitor, use a 0.1F ceramic capac-
itor in parallel with the 4.7F capacitor. Noise on the
reference degrades conversion accuracy.
The input impedance at REF is 40k
for DC currents.
During a conversion the external reference at REF must
deliver 100A of DC load current and have an output
impedance of 10
or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX1062’s equivalent input noise (80VRMS) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/s to complete the required output voltage
change before the beginning of the acquisition time.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sam-
pled voltage has settled before the end of the acquisition
time.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals active dur-
ing input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
14-Bit, +5V, 200ksps ADC with 10A Shutdown
10
______________________________________________________________________________________
COMPLETE CONVERSION SEQUENCE
CONVERSION 0
CONVERSION 1
POWERED UP
POWERED DOWN
DOUT
CS
Figure 7. Shutdown Sequence
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
12
3
0
FS
FS - 3/2LSB
FS = VREF
INPUT VOLTAGE (LSB)
1LSB =
VREF
16384
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
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