- 您现在的位置：买卖IC网 > PDF目录9869 > MAX1068BCEG+ (Maxim Integrated Products)IC ADC 14BIT 200KSPS 24-QSOP PDF资料下载
参数资料
| 型号： | MAX1068BCEG+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/30页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 200KSPS 24-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 位数： | 14 |
| 采样率（每秒）： | 200k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 762mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
MAX1067/MAX1068
Internal Clock 16-Bit-Wide Data-Transfer and
Scan Mode (MAX1068 Only)
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE-interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (see Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris-
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external
clock while the internal clock is on. Turning off SCLK
ensures lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuit-
ry are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1068 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1068 in internal clock mode. Enable scanning by
setting bits 4 and 3 in the command/configuration/con-
trol register (see Tables 3 and 4). In scan mode, conver-
sion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence, EOC transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of EOC. Figure 15 shows the timing dia-
gram for 16-bit-wide data transfer in scan mode.
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
20
______________________________________________________________________________________
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
1
89
16
X = DON
,
T CARE
2
13
17
45
48
64
32
34
X X X X X X X X
DATA
LSB
S1
S0
X
tACQ
POWER-DOWN
tCONV
tACQ
tCONV
MSB
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1068 Only)
相关PDF资料 |
PDF描述 |
|---|---|
| V48A24T500BL3 | CONVERTER MOD DC/DC 24V 500W |
| V48A24T500BG2 | CONVERTER MOD DC/DC 24V 500W |
| VE-27P-MX-F2 | CONVERTER MOD DC/DC 13.8V 75W |
| MC10EP89DR2G | IC DRIVER COAX CBL 5V ECL 8-SOIC |
| VE-27P-MX-F1 | CONVERTER MOD DC/DC 13.8V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1068BCEG+ | 功能描述:模数转换器 - ADC MultiCh 14-Bit 200ksps RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1068BCEG+T | 功能描述:模数转换器 - ADC MultiCh 14-Bit 200ksps RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1068BCEG-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1068BEEG | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1068BEEG+ | 功能描述:模数转换器 - ADC MultiCh 14-Bit 200ksps RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
发布紧急采购，3分钟左右您将得到回复。