- 您现在的位置：买卖IC网 > PDF目录10569 > MAX1077ETC+ (Maxim Integrated Products)IC ADC 10BIT 1.5MSPS 12-TQFN PDF资料下载
参数资料
| 型号： | MAX1077ETC+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/18页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1.5MSPS 12-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 75 |
| 位数： | 10 |
| 采样率（每秒）： | 1.5M |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 22mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WQFN 裸露焊盘 |
| 供应商设备封装： | 12-TQFN-EP（4x4） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极 |
| 产品目录页面： | 1395 (CN2011-ZH PDF) |
MAX1077/MAX1079
1.5Msps, Single-Supply, Low-Power, True-
Differential, 10-Bit ADCs with Internal Reference
_______________________________________________________________________________________
9
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1077/MAX1079 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a con-
version is initiated. SCLK runs the conversion, and the
data can then be shifted out serially on DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures
1 and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence:
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance
to logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the con-
version is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions tDOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 10 data bits, 2 sub-bits (S1 and S0), and 3
leading zeros, at least 16 rising clock edges are need-
ed to shift out these bits. For continuous operation, pull
CNVST high between the 14th and the 16th SCLK ris-
ing edges. If CNVST stays low after the falling edge of
the 16th SCLK cycle, the DOUT line goes to a high-
impedance state on either CNVST’s rising edge or the
next SCLK’s rising edge.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by
placing the MAX1077/MAX1079 in either partial power-
down mode or full power-down mode. Partial power-
down mode is ideal for infrequent data sampling and
fast wake-up time applications. Pull CNVST high after
the 3rd SCLK rising edge and before the 14th SCLK
rising edge to enter and stay in partial power-down
mode (see Figure 6). This reduces the supply current
to 2mA. While in partial power-down mode, the refer-
ence remains enabled to allow valid conversions once
the IC is returned to normal mode. Drive CNVST low
and allow at least 14 SCLK cycles to elapse before dri-
ving CNVST high to exit partial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1077/MAX1079 have to be in partial power-down
mode to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter
RGND
AIN+
GND
DOUT
SCLK
CNVST
CONTROL
LOGIC AND
TIMING
AIN-
VL
VDD
REF
10-BIT
SAR
ADC
MAX1077
MAX1079
T/H
OUTPUT
BUFFER
REF 2.048V
Figure 3. Functional Diagram
CIN+
RIN+
RIN-
CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
ACQUISITION MODE
CIN+
RIN+
RIN-
CIN-
VAZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B5K-IV-F3 | CONVERTER MOD DC/DC 40V 150W |
| VI-252-MX | CONVERTER MOD DC/DC 15V 75W |
| VI-B5K-IV-F2 | CONVERTER MOD DC/DC 40V 150W |
| VI-251-MX | CONVERTER MOD DC/DC 12V 75W |
| VI-B5K-IV-F1 | CONVERTER MOD DC/DC 40V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1077ETC+ | 功能描述:模数转换器 - ADC 10Bit 1.5Msps Single Sply True Diff RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1077ETC+T | 功能描述:模数转换器 - ADC 10Bit 1.5Msps Single Sply True Diff RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1077ETCT | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs with Internal Reference |
| MAX1077ETC-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1078 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1.8Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs with Internal Reference |
发布紧急采购，3分钟左右您将得到回复。