参数资料
型号: MAX107ECS+
厂商: Maxim Integrated Products
文件页数: 6/21页
文件大小: 0K
描述: IC ADC 6BIT 400MSPS DL 80-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 119
位数: 6
采样率(每秒): 400M
数据接口: 并联
转换器数目: 2
功率耗散(最大): 2.6W
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-TQFP 裸露焊盘
供应商设备封装: 80-TQFP-EP(12x12)
包装: 托盘
输入数目和类型: 4 个单端,双极;2 个差分,双极
MAX107
designed for single-ended, low-phase noise sine-wave
clock signals with as little as 500mVp-p amplitude
(-2dBm).
Single-Ended Clock (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase noise sine-wave source into a single
clock input (Figure 4). Essentially, the dynamic perfor-
mance of the converter is unaffected by clock-drive
power levels from -2dBm (500mVp-p clock signal
amplitude) to +10dBm (2Vp-p clock signal amplitude).
The MAX107 dynamic performance specifications are
determined by a single-ended clock drive of -2dBm
(500mVp-p clock signal amplitude). To avoid saturation
of the input amplifier stage, limit the clock power level
to a maximum of +10dBm.
Differential Clock (Sine-Wave Drive)
The advantages of differential clock drive (Figure 5)
can be obtained by using an appropriate balun or
transformer to convert single-ended sine-wave sources
into differential drives. Refer to Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
LVDS, ECL and PECL Clock
The innovative input architecture of the MAX107 clock
also allows these inputs to be driven by LVDS-, ECL- or
PECL-compatible input levels, ranging from 500mVp-p
to 2Vp-p (Figure 6).
Timing Requirements
The MAX107 features a 6:12 demultiplexer, which
reduces the output data rate (including DREADY and
DOR signals) to one-half of the sample clock rate. The
demultiplexed outputs are presented in dual 6-bit two’s
complement format with two consecutive samples in
the primary and auxiliary output ports on the rising
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
14
______________________________________________________________________________________
AGND
B
0
°
0
°
0
°
180
°
D
C
A
SIGNAL SOURCE
50
*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50
TO AGND) ON A
BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
50
AGND
50
*
Figure 3. Single-Ended to Differential Conversion Using a Balun
AGND
FROM SIGNAL SOURCE
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
Figure 4. Single-Ended Clock Input With AC-Coupled Input
Drive (CLK, INI, INQ)
Figure 5. Differential, AC-Coupled Input Drive (CLK, INI, INQ)
AGND
50
TRANSMISSION LINES
TO 50
-TERMINATED
SIGNAL SOURCE
OR BALUN
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
50
50
50
TRANSMISSION LINES
LVDS LINE DRIVER
SIGNAL
SOURCE
INPUT
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
100pF
100
Figure 6. LVDS Input Drive (CLK, INI, INQ)
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相关代理商/技术参数
参数描述
MAX107ECS+ 功能描述:模数转换器 - ADC Dual 6-Bit 400Msps w/OnChip Wdbnd InAmp RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX107ECS+T 功能描述:模数转换器 - ADC Dual 6-Bit 400Msps w/OnChip Wdbnd InAmp RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX107ECS-D 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX107ECS-TD 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
MAX107EVKIT 功能描述:数据转换 IC 开发工具 RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V