参数资料
型号: MAX1081BEUP+T
厂商: Maxim Integrated Products
文件页数: 2/24页
文件大小: 0K
描述: IC ADC 10BIT 300KSPS 20-TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 300k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 8.0mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个差分,单极;4 个差分,双极
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
10
______________________________________________________________________________________
Pin Description
Positive Supply Voltage
VDD2
19
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
VDD1.
REFADJ
12
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
SSTRB
15
Serial Data Input. Data is clocked in at SCLK’s rising edge.
DIN
16
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
CS
17
Serial Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
SCLK
18
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a 2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
VDD1.
REF
11
Analog and Digital Ground
GND
13
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
DOUT
14
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2A
(typ).
SHDN
10
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
COM
9
PIN
Sampling Analog Inputs
CH0–CH7
1–8
FUNCTION
NAME
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
Positive Supply Voltage
VDD1
20
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