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参数资料
| 型号： | MAX1093BEEG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 250KSPS 24-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 10 |
| 采样率（每秒）： | 250k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 762mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个伪差分，单极；2 个伪差分，双极 |
MAX1091/MAX1093
250ksps, +3V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
8
_______________________________________________________________________________________
Pin Description
NAME
1
HBEN
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
2
D7
Three-State Digital I/O Line (D7)
3
D6
Three-State Digital I/O Line (D6)
4
D5
Three-State Digital I/O Line (D5)
5
D4
Three-State Digital I/O Line (D4)
6
D3
Three-State Digital I/O Line (D3)
7
D2
Three-State Digital I/O Line (D2)
8
D1/D9
Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
9
D0/D8
Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
10
INT
INT goes low when the conversion is complete and the output data is ready.
11
RD
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on
the data bus.
12
WR
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
13
CLK
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In
internal clock mode, connect this pin to either VDD or GND.
14
CS
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high imped-
ance.
15
CH7
Analog Input Channel 7
16
CH6
Analog Input Channel 6
17
CH5
Analog Input Channel 5
18
CH4
Analog Input Channel 4
19
CH3
Analog Input Channel 3
20
CH2
Analog Input Channel 2
21
CH1
Analog Input Channel 1
22
CH0
Analog Input Channel 0
23
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
24
GND
Analog and Digital Ground
25
REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
0.01F capacitor. When using an external reference, connect REFADJ to VDD to disable
the internal bandgap reference.
26
REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7F capacitor to
GND when using the internal reference.
27
VDD
Analog +5V Power Supply. Bypass with a 0.1F capacitor to GND.
28
VLOGIC
Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can
range from +1.8V to VDD + 300mV.
1
2
PIN
3
4
5
6
7
8
9
10
11
12
13
14
—
15
16
17
18
19
20
21
22
23
24
FUNCTION
MAX1091
MAX1093
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