参数资料
型号: MAX11044ETN+T
厂商: Maxim Integrated Products
文件页数: 3/28页
文件大小: 0K
描述: ADC 16BIT SAMPLING 4CH 56-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 16
采样率(每秒): 250k
数据接口: 并联
转换器数目: 4
功率耗散(最大): 3.81W
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(8x8)
包装: 带卷 (TR)
输入数目和类型: 4 个单端,双极
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
11
Maxim Integrated
MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
Pin Description (continued)
MAX11044/
MAX11044B
(TQFN-EP)
MAX11045/
MAX11045B
(TQFN-EP)
MAX11046/
MAX11046B
(TQFN-EP)
NAME
FUNCTION
24, 30, 41, 47
AVDD
Analog Supply Input. Bypass AVDD to AGND with a
0.1μF capacitor at each AVDD input.
25, 31, 40, 46
AGND
Analog Ground. Connect all AGND inputs together.
32
29
26
CH0
Channel 0 Analog Input
34
32
29
CH1
Channel 1 Analog Input
37
34
32
CH2
Channel 2 Analog Input
39
37
34
CH3
Channel 3 Analog Input
36
REFIO
External Reference Input/Internal Reference Output.
Place a 0.1μF capacitor from REFIO to AGND.
39
37
CH4
Channel 4 Analog Input
42
39
CH5
Channel 5 Analog Input
42
CH6
Channel 6 Analog Input
45
CH7
Channel 7 Analog Input
52
WR
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
53
54
CS
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
54
RD
Active-Low Read Input. Drive RD low to read from the
ADC. Each rising edge of RD advances the channel
output on the data bus.
55
DB15
16-Bit Parallel Data Bus Digital Output Bit 15
56
DB14
16-Bit Parallel Data Bus Digital Output Bit 14
26, 29, 42, 45
26, 45
I.C.
Internally Connected. Connect to AGND.
——
EP
Exposed Pad. Internally connected to AGND. Connect to
a large ground plane to maximize thermal performance.
Not intended as an electrical connection point.
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