参数资料
型号: MAX1108CUB+
厂商: Maxim Integrated Products
文件页数: 8/20页
文件大小: 0K
描述: IC ADC 8BIT LP 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
位数: 8
采样率(每秒): 50k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 444mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-µMAX
包装: 管件
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个伪差分,单极;1 个伪差分,双极
MAX1108/MAX1109
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
16
______________________________________________________________________________________
to the SCLK pin; varying the analog input alters the
result of conversion that is clocked out at the DOUT pin.
A total of 10 clock cycles is required per conversion.
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte.
Acquisition starts on the falling edge of the fourth SCLK
and lasts for two SCLKs in external clock mode or four
SCLKs in internal clock mode. Conversion starts imme-
diately after acquisition is completed. The start bit is
defined as:
The first high bit clocked into DIN with CS
low any time the converter is idle; e.g., after
VDD is applied.
OR
In external clock mode, the first high bit
clocked into DIN after the bit 5 (D5) of a con-
version in progress is clocked onto the
DOUT pin.
OR
In internal clock mode, the first high bit
clocked into DIN after the bit 4 (D4) is
clocked onto the DOUT pin.
The MAX1108/MAX1109 can run at a maximum speed
of 10 clocks per conversion. Figure 10 shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion is
typically the fastest that a microcontroller can drive the
MAX1108/MAX1109. Figure 11 shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
SCLK
DIN
DOUT
CS
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
D7
D5
D0
D7
D5
D0
D7
CONVERSION RESULT 1
CONTROL BYTE 2
S
1
810
1
10
1
10
1
S
tACQ
IDLE
A/D STATE
tCONV
Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing
SCLK
DIN
DOUT
CS
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
D7
D0
D7
D0
CONVERSION RESULT 1
S
1
817
25
Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing
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