参数资料
型号: MAX1116EKA+T
厂商: Maxim Integrated Products
文件页数: 12/12页
文件大小: 0K
描述: IC ADC 8BIT SERIAL SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
位数: 8
采样率(每秒): 100k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 910µW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
输入数目和类型: 1 个单端,单极
产品目录页面: 1395 (CN2011-ZH PDF)
其它名称: MAX1116EKA+TDKR
After CNVST is brought low, allow 7.5s for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked out,
DOUT goes high impedance (100ns to 500ns after the
rising edge) of the eighth SCLK pulse.
SCLK is ignored during the conversion process. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST during an
MAX1115/MAX1116
Single-Supply, Low-Power, Serial 8-Bit ADCs
_______________________________________________________________________________________
9
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE LOW
CH0
tCSH
tCONV
tcp
tccs
tCSL
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
VDD
2
VDD
2
Figure 6c. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle Low
ACTIVE
POWER-DOWN MODE
CNVST
SCLK
DOUT
CH0
IDLE HIGH
CH0
tCSH
tCONV
tcp
tccs
tcsl
tchz
tcl
tcd
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
tcsd
tch
VDD
2
VDD
2
Figure 6d. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle High
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