参数资料
型号: MAX1118EKA+T
厂商: Maxim Integrated Products
文件页数: 13/14页
文件大小: 0K
描述: IC ADC 8-BIT 100KSPS SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
位数: 8
采样率(每秒): 100k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 680µW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
输入数目和类型: 2 个单端,单极
产品目录页面: 1395 (CN2011-ZH PDF)
其它名称: MAX1118EKA+TDKR
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
8
_______________________________________________________________________________________
VDD
I/O
SCK (SK)
MISO (SI)
GND
DOUT
SCLK
CNVST
GND
VDD
0.1
μF
1
μF
CH0
REF*
* MAX1118 ONLY
1
μF
ANALOG
INPUTS
MAX1117
MAX1118
MAX1119
CPU
VDD
CH1
Figure 3. Typical Operating Circuit
GND
CHOLD
CAPACITIVE DAC
COMPARATOR
16pF
RIN
6.5k
Ω
AUTOZERO
RAIL
TRACK
HOLD
CH0
CH1
Figure 4. Equivalent Input Circuit
Detailed Description
The MAX1117/MAX1118/MAX1119 ADCs use a suc-
cessive-approximation conversion technique and input
T/H circuitry to convert an analog signal to an 8-bit digi-
tal output. The SPI/QSPI/MICROWIRE compatible inter-
face directly connects to microprocessors (Ps) without
additional circuity (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in Figure
4’s equivalent-input circuit and is composed of the T/H,
the input multiplexer, the input comparator, the
switched capacitor DAC, and the auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog
inputs (CH0, CH1) are connected to the holding capac-
itor (CHOLD). Once the acquisition has completed, the
T/H switch opens and CHOLD is connected to GND,
retaining the charge on CHOLD as a sample of the sig-
nal at the analog input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance <1.5k
Ω is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs will also improve the accu-
racy of an input sample.
Conversion Process
The MAX1117/MAX1118/MAX1119 conversion process
is internally timed. The total acquisition and conversion
process takes <7.5s. Once an input sample has been
acquired, the comparator’s negative input is then con-
VDD
3k
Ω
CLOAD
GND
DOUT
CLOAD
GND
3k
Ω
DOUT
a) VOL TO VOH
b) HIGH-Z to VOL AND VOH to VOL
VDD
3k
Ω
CLOAD
GND
DOUT
CLOAD
GND
3k
Ω
DOUT
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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