参数资料
型号: MAX11205AEUB+T
厂商: Maxim Integrated Products
文件页数: 2/14页
文件大小: 0K
描述: IC ADC 16BIT SRL 120SPS 10UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 16
采样率(每秒): 120
数据接口: 串行
转换器数目: 1
功率耗散(最大): 444mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-µMAX
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
10 _____________________________________________________________________________________
MAX11205
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Data Read Following Every Conversion
The MAX11205 indicates conversion data availability, as
well as allows the retrieval of data through the RDY/DOUT
output. The RDY/DOUT output idles at the value of the
last bit read unless a 25th SCLK pulse is provided, caus-
ing RDY/DOUT to idle high. RDY/DOUT is pulled low
when the conversion data is available.
Figure 1 shows the timing diagram for the data read.
Once a low is detected on RDY/DOUT, clock pulses at
SCLK clock out the data. Data is shifted out MSB first
and is in binary two’s complement format. Once all the
data has been shifted out, a 25th SCLK is required to
pull the RDY/DOUT output back to the idle high state.
See Figure 2.
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
Data Read Followed by Self-Calibration
To initiate self-calibration at the end of a data read,
provide a 26th SCLK pulse. After reading the 16 bits of
conversion data, a 25th positive edge on SCLK pulls the
RDY/DOUT output back high, indicating the end of data
read. Provide a 26th SCLK pulse to initiate a self-calibra-
tion routine starting on the falling edge of the 26th SCLK.
A subsequent falling edge of RDY/DOUT indicates data
availability at the end of calibration. The timing is illus-
trated in Figure 3.
Data Read Followed by Sleep Mode
The MAX11205 can be put into sleep mode to save
power between conversions. To activate the sleep mode,
idle the SCLK high any time after the RDY/DOUT output
goes low (that is, after conversion data is available). It is
not required to read out all 16 bits before putting the part
in sleep mode. Sleep mode is activated after the SCLK is
held high (see Figure 4). The RDY/DOUT output is pulled
high once the device enters sleep mode. To come out
of the sleep mode, pull SCLK low. After the sleep mode
is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low, indicating the
next conversion data is available. See Figure 4.
Single-Conversion Mode
For operating the MAX11205 in single-conversion mode,
activate and deactivate sleep mode between conver-
sions as described in the Data Read Followed by Sleep
Mode section). Single-conversion mode reduces power
consumption by shutting down the device when idle
between conversions. See Figure 4.
Single-Conversion Mode
with Self-Calibration at Wake-Up
The MAX11205 can be put in self-calibration mode imme-
diately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration, and when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with self-
calibration.
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