参数资料
型号: MAX11211EEE+T
厂商: Maxim Integrated Products
文件页数: 6/27页
文件大小: 0K
描述: ADC 18BIT DELTA-SIGMA 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 18
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 667mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
输入数目和类型: *
14
Maxim Integrated
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11209/MAX11211
Figure 5. SPI Command Byte
Figure 6. SPI Register Access Write
Serial-Digital Interface
The MAX11209/MAX11211 interface is fully compatible
with SPI-, QSPI-, and MICROWIRE-standard serial inter-
faces. The SPI interface provides access to nine on-chip
registers that are 8 or 24 bits wide.
Drive CS low to transfer data in and out of the devices.
Clock in data at DIN on the rising edge of SCLK. The
RDY/DOUT output serves two functions: conversion sta-
tus and data read. To find the conversion status, assert
CS low and read the RDY/DOUT output; the conversion
is in progress if the RDY/DOUT output reads logic-high
and the conversion is complete if the RDY/DOUT output
reads logic-low. Data at RDY/DOUT changes on the
falling edge of SCLK and is valid on the rising edge of
SCLK. DIN and DOUT are transferred MSB first. Drive
CS high to force DOUT high impedance and cause
the devices to ignore any signals on SCLK and DIN.
Connect CS low for 3-wire operation. Figures 5, 6, and 7
show the SPI timing diagrams.
tCSH0
tDOE
HIGH-Z
tDOD
HIGH-Z
tCSS0
SCLK
0
X
1
10
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0
8
DIN
tDH
tCP
tCSH1
tCSS1
tCSW
tCL tCH
tDS
CS
RDY/DOUT
tCSH0
tDOE
HIGH-Z
tDOD
HIGH-Z
tCSS0
SCLK
0
X
1
11
X
RS3
RS2
RS1
RS0
W/R
D7
D6
D5
D4
D3
D2
D1
D0
16
89
DIN
tDH
tCP
tCSH1
tCSS1
tCSW
tCL
tCH
tDS
CS
RDY/DOUT
SPI REGISTER ACCESS WRITE
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