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参数资料
| 型号： | MAX1125 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | 8-Bit, 300Msps Flash ADC |
| 中文描述： | 8位，300Msps闪速ADC |
| 文件页数： | 6/12页 |
| 文件大小： | 114K |
| 代理商： | MAX1125 |
M
The MAX1125 has true differential analog and digital
data paths from the preamplifiers to the output buffers
(Current-Mode Logic) for reducing potential missing
codes while rejecting common-mode noise.
Careful layout of the analog circuitry reduces signature
errors. Every comparator also has a clock buffer to
reduce differential delays and to improve signal-to-
noise ratio. The output-drive capability of the device
can provide full ECL swings into 50
loads.
___________Typic al Interfac e Circ uit
Figure 1 shows the typical interface circuit. The
MAX1125 is relatively easy to apply depending on the
accuracy needed. Wire-wrap may be employed with
careful point-to-point ground connections if desired,
but a double-sided PC board with a ground plane on
the component side, separated into digital and analog
sections, gives the best performance. The converter is
bonded-out to place the digital pins on the left side of
the package and the analog pins on the right side. Ad-
ditionally, an RF bead connection through a single
point from the analog to digital ground planes reduces
ground noise pickup.
Figure 2 (CERQUAD package only) shows the most
elaborate method of achieving the least error by cor-
recting for integral nonlinearity, input induced distor-
tion, and power-supply/ground noise. It uses external
reference ladder tap connections, an input buffer, and
supply decoupling. The function of each pin and exter-
nal connections to other components is as follows:
V
EE
, AGND, DGND
V
is the supply pin with AGND as ground for the
device. The power-supply pins should be bypassed as
close to the device as possible with at least a 0.01μF
ceramic capacitor. A 1μF tantalum should also be used
for low-frequency suppression. DGND is the ground for
the ECL outputs and should be referenced to the output
pulldown voltage and bypassed as shown in Figure 1.
Analog Input V IN
There are two analog input pins that are tied to the
same point internally. Either one may be used as an
analog input sense and the other for input force. This is
convenient for testing the source signal to see if there is
sufficient drive capability. The pins can also be tied to-
gether and driven by the same source. The MAX1125 is
superior to similar devices due to a preamplifier stage
before the comparators (Figure 4). This makes the
device easier to drive because it has constant capaci-
tance and induces less slew-rate distortion. An optional
input buffer may be used.
Cloc k Inputs CLK ,
CLK
The clock inputs are designed to be driven differentially
with ECL levels. Because
CLK
is internally biased to -1.3V,
the clock may be driven single-ended (Figure 5).
CLK
may be left open, but a 0.01μF bypass capacitor from
CLK
to AGND is recommended. NOTE: System perfor-
mance may be degraded due to increased noise or jitter.
Output Logic Control MINV , LINV
These are ECL-compatible digital controls for changing
the output code from straight binary to two's comple-
ment, etc. (Table 1 and Figure 4). Both MINV and LINV
are in the logic low (0) state when left open. The high
state can be obtained by tying to AGND through a
diode or 3.9k
resistor.
Digital Outputs D0 to D7
The digital outputs can drive ECL levels into 50
when
pulled down to -2V. When pulled down to -5.2V, the
outputs can drive 150
to 1k
loads.
Referenc e Inputs V RBF, V R2, V RT F
There are two reference inputs and one external refer-
ence voltage tap. These are -2V (VRBF), mid-tap (VR2)
and AGND (VRTF). The reference pins can be driven
as shown in Figure 1. VR2 should be bypassed to
AGND for further noise suppression.
Reference Inputs VRBF, VRBS, VR1, VR2,
VR3, VRTF, VRTS (CERQUAD package only)
These are five external reference voltage taps from -2V
(VRBF) to AGND (VRTF) that can be used to control inte-
gral linearity over temperature. The taps can be driven by
8-Bit, 300Msps Flash ADC
6
_______________________________________________________________________________________
Table 1. Output Coding
MINV
LINV
0
0
0
1
1
0
1
1
0V
.
.
.
111...11
111...10
.
.
100...00
100...01
.
.
011...11
011...10
.
.
000...00
000...01
.
.
.
.
.
.
.
.
.
011...11
000...00
111...11
100...00
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
-2V
000...00
011...11
100...00
111...11
000...01
011...10
100...01
111...10
100...00
111...11
000...00
011...11
1: V
IH,
V
OH
0: V
IL,
V
OL
V
IN
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