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参数资料
| 型号： | MAX1127 |
| 厂商： | Maxim Integrated Products, Inc. |
| 元件分类： | 串行ADC |
| 英文描述： | Quad, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs |
| 中文描述： | 四路、12位、65Msps、1.8V ADC，串行LVDS输出 |
| 文件页数： | 15/25页 |
| 文件大小： | 1661K |
| 代理商： | MAX1127 |
M
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
______________________________________________________________________________________
15
PIN
NAME
FUNCTION
29
SLVS/
LVDS
Differential Output Signal Format Select Input. Drive SLVS/
LVDS
high to select SLVS outputs. Drive
SLVS/
LVDS
low to select LVDS outputs.
30
31
32
33
PLL0
PLL1
PLL2
PLL3
PLL Control Input 0. PLL0 is reserved for factory testing only and must always be connected to GND.
PLL Control Input 1. PLL1 is reserved for factory testing only and must always be connected to GND.
PLL Control Input 2. See Table 1 for details.
PLL Control Input 3. See Table 1 for details.
34, 37, 40,
43, 46, 49,
52
OV
DD
Output-Driver Power Input. Connect OV
DD
to a 1.7V to 1.9V power supply. Bypass each OV
DD
to
GND with a 0.1μF capacitor as close to the device as possible. Bypass the OV
DD
power plane to the
GND ground plane with a bulk
≥
2.2μF capacitor as close to the device as possible. Connect all OV
DD
pins to the same potential.
35
36
38
39
OUT3N
OUT3P
OUT2N
OUT2P
Channel 3 Negative LVDS/SLVS Output
Channel 3 Positive LVDS/SLVS Output
Channel 2 Negative LVDS/SLVS Output
Channel 2 Positive LVDS/SLVS Output
41
FRAMEN
Negative Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
42
FRAMEP
Positive Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to
a valid D0 in the output data stream.
44
45
47
48
50
51
CLKOUTN
CLKOUTP
OUT1N
OUT1P
OUT0N
OUT0P
Negative LVDS/SLVS Serial Clock Output
Positive LVDS/SLVS Serial Clock Output
Channel 1 Negative LVDS/SLVS Output
Channel 1 Positive LVDS/SLVS Output
Channel 0 Negative LVDS/SLVS Output
Channel 0 Positive LVDS/SLVS Output
53
PD0
Channel 0 Power-Down Input. Drive PD0 high to power-down channel 0. Drive PD0 low for normal
operation.
54
PD1
Channel 1 Power-Down Input. Drive PD1 high to power-down channel 1. Drive PD1 low for normal
operation.
55
PD2
Channel 2 Power-Down Input. Drive PD2 high to power-down channel 2. Drive PD2 low for normal
operation.
56
PD3
Channel 3 Power-Down Input. Drive PD3 high to power-down channel 3. Drive PD3 low for normal
operation.
57
PDALL
Global Power-Down Input. Drive PDALL high to power-down all channels and reference. Drive PDALL
low for normal operation.
63
T
/B
Output Format Select Input. Drive
T
/B high to select binary output format. Drive
T
/B low to select two’s
complement output format.
Pin Description (continued)
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