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| 型号： | MAX1149BEUP+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 116KSPS 20-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 74 |
| 位数： | 14 |
| 采样率（每秒）： | 116k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 879mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
| 产品目录页面： | 1395 (CN2011-ZH PDF) |
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
12
______________________________________________________________________________________
Detailed Description
The MAX1146–MAX1149 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy inter-
face to microprocessors (Ps). Figure 4 shows the typi-
cal application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
True-Differential Analog Input and
Track/Hold
The MAX1146–MAX1149 analog input architecture con-
tains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
CT/H+ and CT/H- track the analog input signal. At the
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retain-
ing the charge on CT/H+ and CT/H- as a sample of the
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF
× (VIN+ - VIN-) from
CT/H+ and CT/H- to the binary-weighted capacitive
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is com-
plete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisi-
tion time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (tACQ) in which the T/H capacitance
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (RSOURCE) should be mini-
mized to allow the T/H capacitance to charge within
this allotted time.
tACQ = 11.5
× (RSOURCE + RIN) × CIN
where RSOURCE is the analog input source impedance,
RIN is 2.6k
(which is the sum of the analog input MUX
and T/H switch resistances), and CIN is 18pF (which is
the sum of CT/H+, CT/H-, and input stray capacitance).
To minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
MAX1148
MAX1149
SCLK
DIN
DOUT
SSTRB
VDD
VSS
REFADJ
COM
ANALOG
INPUTS
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
REF
AGND
DGND
0.01
F
0.1
F4.7F
2.2
F
P
I/O
SCK
MOSI
MISO
10
SHDN
CS
Figure 4. Typical Application Circuit
MAX1149
ANALOG
INPUT
MUX
CONTROL
LOGIC
INTERNAL
CLOCK
INPUT
SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
+1.250V
BANDGAP
REFERENCE
T/H
DOUT
SSTRB
VDD
AGND
SCLK
DIN
COM
REFADJ
REF
CH6
CH7
CH4
CH5
CH1
CH2
CH3
CH0
DGND
SAR
ADC
REF
CLOCK
IN
OUT
20k
AV = 2.0V/V
CS
SHDN
Figure 5. Functional Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1149BEUP+ | 功能描述:模数转换器 - ADC 14-Bit 8Ch 116ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1149BEUP+T | 功能描述:模数转换器 - ADC 14-Bit 8Ch 116ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1149BEUP-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1149CGP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
| MAX1149CUP | 制造商:Maxim Integrated Products 功能描述:MULTICHANNEL, TRUE-DIFFERENTIAL, SERIAL, 14-B - Rail/Tube |
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