参数资料
型号: MAX11619EEE+
厂商: Maxim Integrated Products
文件页数: 9/21页
文件大小: 0K
描述: IC ADC 10BIT SRL 300KSPS 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
位数: 10
采样率(每秒): 300k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 667mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
输入数目和类型: 4 个单端,单极
MAX11618–MAX11621/MAX11624/MAX11625
10-Bit, 300ksps ADCs
with FIFO and Internal Reference
______________________________________________________________________________________
17
Power-Up Default State
The MAX11618–MAX11621/MAX11624/MAX11625
power up with all blocks in shutdown, including the ref-
erence. All registers power up in state 00000000,
except for the setup register, which powers up in clock
mode 10 (CKSEL1 = 1).
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11618–MAX11621/MAX11624/MAX11625. The 10-
bit conversion result is output in MSB-first format with
four leading zeros followed by 10-bit data and two trail-
ing zeros. DIN data is latched into the serial interface
on the rising edge of SCLK. Data on DOUT transitions
on the falling edge of SCLK. Conversions in clock
modes 00 and 01 are initiated by CNVST. Conversions
in clock modes 10 and 11 are initiated by writing an
input data byte to the conversion register. Data output
is binary.
Internally Timed Acquisitions and
Conversions Using
CNVST
Performing Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11618–
MAX11621/MAX11624/MAX11625 then wake up, scan
all requested channels, store the results in the FIFO,
and shut down. After the scan is complete, EOC is
pulled low and the results are available in the FIFO.
Wait until EOC goes low before pulling CS low to com-
municate with the serial interface. EOC stays low until
CS or CNVST is pulled low again.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with
CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4s to complete the acquisition. If the internal
reference needs to wake up, an additional 65s is
required for the internal reference to power up.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. The result is available on
DOUT once EOC has been pulled low.
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
DOUT
MSB1
LSB1
MSB2
SCLK
CNVST
EOC
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Figure 4. Clock Mode 00
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