- 您现在的位置：买卖IC网 > PDF目录9975 > MAX11644EUA+T (Maxim Integrated Products)IC ADC 12BIT SERIAL 8-UMAX PDF资料下载
参数资料
| 型号： | MAX11644EUA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SERIAL 8-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 94.4k |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 362mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；2 个单端，双极；1 个差分，单极；1 个差分，双极 |
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
16
______________________________________________________________________________________
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing a
START condition followed by seven address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11644/MAX11645 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 4 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s), it
can issue an acknowledge if it wants to continue read-
ing or a not-acknowledge if it no longer wishes to read.
If the MAX11644/MAX11645 receive a not-acknowl-
edge, they release SDA, allowing the master to generate
a STOP or a repeated START condition. See the
Clock
Modes and Scan Mode sections for detailed information
on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11644/MAX11645 are defaulted
to internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11644/MAX11645 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11644/MAX11645 begin tracking the analog input
after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11644/
MAX11645 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11644/
MAX11645 contain two 12-bit blocks of memory. Once
all conversions are complete, the MAX11644/
MAX11645 release SCL, allowing it to be pulled high.
The master can now clock the results out of the memo-
ry in the same order the scan conversion has been
done at a clock rate of up to 1.7MHz. SCL is stretched
for a maximum of 8.3μs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX11644/MAX11645 release SCL.
The converted results are read back in a first-in-first-out
(FIFO) sequence. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and points to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
CLOCK STRETCH
B) SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
A
71 1
R
CLOCK STRETCH
NUMBER OF BITS
P OR Sr
1
8
RESULT 8 LSBs
8
RESULT 4 MSBs
A
1
A) SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
71 1
R
NUMBER OF BITS
P OR Sr
1
8
RESULT 1 ( 4MSBs)
A
1
A
8
RESULT 1 (8 LSBs) A
8
RESULT N (8LSBs)
A
1
8
RESULT N (4MSBs)
SLAVE TO MASTER
MASTER TO SLAVE
CLOCK STRETCH
tACQ1
tCONV2
tACQ2
tCONVN
tACQN
tCONV
tACQ
1
tCONV1
Figure 10. Internal Clock Mode Read Cycles
相关PDF资料 |
PDF描述 |
|---|---|
| IDT72265LA15TFI8 | IC FIFO 8KX18 LP 15NS 64QFP |
| MS3100E28-15S | CONN RCPT 35POS WALL MNT W/SCKT |
| MS3102R36-5PX | CONN RCPT 4POS BOX MNT W/PINS |
| VE-B13-MW-F3 | CONVERTER MOD DC/DC 24V 100W |
| VE-B13-MW-F2 | CONVERTER MOD DC/DC 24V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX11645EUA+ | 功能描述:模数转换器 - ADC 12-Bit 2Ch 94.4ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX11645EUA+T | 功能描述:模数转换器 - ADC 12-Bit 2Ch 94.4ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX11645EWC+ | 制造商:Maxim Integrated Products 功能描述: |
| MAX11645EWC+T | 功能描述:模数转换器 - ADC 12-Bit 2Ch 94.4ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX11646 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 10-Bit ADCs |
发布紧急采购，3分钟左右您将得到回复。