参数资料
型号: MAX11647EWC+T
厂商: Maxim Integrated Products
文件页数: 7/22页
文件大小: 0K
描述: IC ADC 10BIT I2C 94.4KSPS 12WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 94.4k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 362mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFBGA,WLCSP
供应商设备封装: 12-WLP
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个差分,单极;1 个差分,双极
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________
15
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11646/MAX11647 (slave) issue an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 6 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s),
it can issue an acknowledge if it wants to continue
reading or a not-acknowledge if it no longer wishes to
read. If the MAX11646/MAX11647 receive a not-
acknowledge, they release SDA, allowing the master to
generate a STOP or a repeated START condition. See
the
Clock Modes and Scan Mode sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11646/MAX11647 are defaulted
to internal clock mode (CLK = 0).
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SCAN1
SCAN0
X
CS0
SGL/
DIF
BIT
NAME
DESCRIPTION
7
REG
Register bit. 1= setup byte (see Table 1), 0 = configuration byte.
6
SCAN1
5
SCAN0
Scan-select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.
4
X
3
X
2
X
1
CS0
Channel-select bit. CS0 selects which analog input channels are to be used for conversion
(Tables 3 and 4). Defaults to 0000 at power-up.
0
SGL/
DIF
1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-
Ended/Differential Input section.
Table 2. Configuration Byte Format
CS0
AIN0
AIN1
GND
0
+
-
1
+
-
Table 3. Channel Selection in Single-
Ended Mode (SGL/DIF = 1)
CS0
AIN0
AIN1
0
+
-
1
-
+
Table 4. Channel Selection in Differential
Mode (SGL/DIF = 0)
X = Don’t care.
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