参数资料
型号: MAX1174BCUP+T
厂商: Maxim Integrated Products
文件页数: 13/15页
文件大小: 0K
描述: IC ADC 14BIT 135KSPS 20-TSSOP
标准包装: 2,500
位数: 14
采样率(每秒): 135k
数据接口: 并联
转换器数目: 1
功率耗散(最大): 879mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
输入数目和类型: 1 个单端,双极
Detailed Description
Converter Operation
The MAX1156/MAX1158/MAX1174 use a successive-
approximation (SAR) conversion technique with an
inherent track-and-hold (T/H) stage to convert an ana-
log input into a 14-bit digital output. Parallel outputs
provide a high-speed interface to microprocessors
(Ps). The Functional Diagram shows a simplified inter-
nal architecture of the MAX1156/MAX1158/MAX1174.
Figure 3 shows a typical application circuit for the
MAX1156/MAX1158/MAX1174.
Analog Input
Input Scaler
The MAX1156/MAX1158/MAX1174 have an input
scaler, which allows conversion of true bipolar input
voltages and input voltages greater than the power
supply, while operating from a single +5V analog sup-
ply. The input scaler attenuates and shifts the analog
input to match the input range of the internal DAC. The
MAX1156 has a unipolar input voltage range of 0 to
+10V. The MAX1158 input voltage range is ±10V while
the MAX1174 input voltage range is ±5V. Figure 4
shows the equivalent input circuit of the MAX1156/
MAX1158/MAX1174. This circuit limits the current going
into or out of AIN to less than 1.8mA.
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
(AIN) charges capacitor CHOLD. The acquisition ends
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on CHOLD rep-
resents a sample of the input. In hold mode, the capac-
itive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of 14-bit resolution. Force CS low to put valid
data on the bus after conversion is complete.
MAX1156/MAX1158/MAX1174
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
_______________________________________________________________________________________
7
Pin Description (continued)
PIN
NAME
FUNCTION
13
HBEN
High-Byte Enable Input. Used to multiplex the 14-bit conversion result.
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
14
CS
Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
15
DGND
Digital Ground
16
DVDD
Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND.
17
D0/D8
Three-State Digital Data Output. D0 is the LSB.
18
D1/D9
Three-State Digital Data Output
19
D2/D10
Three-State Digital Data Output
20
D3/D11
Three-State Digital Data Output
DGND
1mA
CLOAD = 20pF
DO–D13
CLOAD = 20pF
1mA
DGND
DVDD
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Figure 1. Load Circuits
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