参数资料
型号: MAX1193ETI+T
厂商: Maxim Integrated Products
文件页数: 17/26页
文件大小: 0K
描述: IC ADC 8BIT 45MSPS DL 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 8
采样率(每秒): 45M
数据接口: 并联
转换器数目: 2
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
输入数目和类型: 4 个单端,双极;2 个差分,双极
MAX1193
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1 is the fundamental amplitude, and V2–V6 are
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1
±f2), (2 x f1), (2 x f2), (2 x f1 ±f2), (2 x f2
±f1). The individual input tone levels are at -7dB FS.
Third-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodula-
tion product relative to the input power of either input
tone when two tones, f1 and f2, are present at the
inputs. The third-order intermodulation products are (2
x f1
±f2), (2 x f2 ±f1). The individual input tone levels
are at -7dB FS.
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supplies are moved
±5%.
Small-Signal Bandwidth
A small -20dB FS analog input signal is applied to an
ADC in such a way that the signal’s slew rate will not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
THD
VVVV
V
log
+++
+
20
2
3
2
4
2
5
2
6
2
1
Ultra-Low-Power, 45Msps, Dual 8-Bit ADC
24
______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 7925
PROCESS: CMOS
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