参数资料
型号: MAX1225ETC+T
厂商: Maxim Integrated Products
文件页数: 6/18页
文件大小: 0K
描述: IC ADC 12BIT 1.5MSPS 12-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 12
采样率(每秒): 1.5M
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 18mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WQFN 裸露焊盘
供应商设备封装: 12-TQFN-EP(4x4)
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
This setup allows continuous conversions provided that
the data-transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the VL
pin to the TMS320C54_ supply voltage when the
MAX1224/MAX1225 are operating with an analog sup-
ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple-
ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.
Another method of connecting the MAX1224/MAX1225
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16, where serial clock (CLOCK) drives the
CLKR, and SCLK and the convert signal (CONVERT)
drive the FSR and CNVST.
The serial port must be set up to accept an external
receive-clock and external receive-frame sync.
MAX1224/MAX1225
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
14
______________________________________________________________________________________
SCLK
DOUT
916
8
1
D2
D11
D10
D8
D7
D6
D5
D4
D3
D9
HIGH-Z
CNVST
D1
D0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
DOUT
SCLK
CNVST
0
1
14
16
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
SCLK
DOUT
CNVST
16
D0
D1
D11
D10
D6
D7
D8
D5
D4
D3
D2
HIGH-Z
D9
HIGH-Z
2
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