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参数资料
| 型号： | MAX1229BCEP+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12-BIT 300KSPS 20-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 300k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 727mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-QSOP |
| 包装： | 管件 |
| 输入数目和类型： | 12 个单端，单极；12 个单端，双极；6 个差分，单极；6 个差分，双极 |
MAX1227/MAX1229/MAX1231
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
______________________________________________________________________________________
19
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100s. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, or if an external ref-
erence is selected but a temperature measurement is
being requested, wait 65s with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a tem-
perature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte. The temperature result
appears on DOUT during the last 2 bytes of the 192
cycles.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = VREF / 2.5V for
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. Board layout should ensure that digital
and analog signal lines are separated from each other.
Do not run analog and digital (especially clock) signals
parallel to one another or run digital lines underneath the
MAX1227/MAX1229/MAX1231 package. High-frequen-
cy noise in the VDD power supply can affect perfor-
mance. Bypass the VDD supply with a 0.1F capacitor
to GND, close to the VDD pin. Minimize capacitor lead
lengths for best supply-noise rejection. If the power sup-
ply is very noisy, connect a 10
resistor in series with
the supply to improve power-supply filtering. For the
TQFN package, connect its exposed pad to ground.
CS
DOUT
SCLK
DIN
EOC
MSB1
LSB1
MSB2
(ACQUISITION1)
(ACQUISITION2)
(CONVERSION1)
(CONVERSION BYTE)
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11
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相关代理商/技术参数 |
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| MAX1229BCEP+ | 功能描述:模数转换器 - ADC 12-Bit 12Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1229BCEP+T | 功能描述:模数转换器 - ADC 12-Bit 12Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1229BCEP-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1229BEEP | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1229BEEP+ | 功能描述:模数转换器 - ADC 12-Bit 12Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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