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| 型号： | MAX1236 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| 中文描述： | 2.7V至3.6V及4.5V至5.5V、低功耗、4/12通道、2线串口12位ADC |
| 文件页数： | 5/22页 |
| 文件大小： | 407K |
| 代理商： | MAX1236 |
M
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
B
= 400pF, Note 11)
Serial Clock Frequency
f
SCLH
Hold Time, Repeated START
Condition (Sr)
(Note 12)
1.7
MHz
t
HD,
STA
160
ns
Low Period of the SCL Clock
High Period of the SCL Clock
t
LOW
t
HIGH
320
120
ns
ns
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160
ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
t
HD
,
DAT
t
SU
,
DAT
(Note 10)
0
10
150
ns
ns
t
RCL
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
- 0.7V
DD
20
160
ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
FCL
t
RDA
t
FDA
t
SU
,
STO
C
B
t
SP
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
Measured from 0.3V
DD
- 0.7V
DD
20
20
20
160
80
160
160
ns
ns
ns
ns
pF
ns
400
10
(Notes 10 and 12)
0
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX1237/MAX1239), V
DD
= 4.5V to 5.5V (MAX1236/MAX1238), V
REF
= 2.048V (MAX1237/MAX1239), V
REF
=
4.096V (MAX1236/MAX1238), C
REF
= 0.1μF, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25
°
C, see Tables 1
–
5 for programming notation.)
Note 1:
For DC accuracy, the MAX1136/MAX1138 are tested at V
DD
= 5V and the MAX1137/MAX1139 are tested at V
DD
= 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3:
Offset nulled.
Note 4:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6:
The absolute input-voltage range for the analog inputs (AIN0
–
AIN11) is from GND to V
DD
.
Note 7:
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.01μF capacitor.
Note 8:
ADC performance is limited by the converter
’
s noise floor, typically 300μV
P-P
.
Note 9:
Measured as for the MAX1237/MAX1239
V
V
V
V
V
V
V
FS
FS
REF
N
(3 6
)
2 7
)
(3 6
.
)
2
1
2 7
[
]
×
相关PDF资料 |
PDF描述 |
|---|---|
| MAX1237 | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| MAX1238 | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| MAX1237MEUA | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| MAX1236MEUA | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| MAX1236LEUA | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
相关代理商/技术参数 |
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