参数资料
型号: MAX1240AESA/V+T
厂商: Maxim Integrated Products
文件页数: 4/15页
文件大小: 0K
描述: IC ADC 12BIT SRL 73KSPS 8SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 12
采样率(每秒): 73k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 471mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
MAX1240/MAX1241
+2.7V, Low-Power,
12-Bit Serial ADCs in 8-Pin SO
12
______________________________________________________________________________________
5) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion’s end, wait for the minimum acquisi-
tion time, tACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with one leading 1, and trailing 0s.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Wait
until DOUT goes high or until the maximum specified
7.5s conversion time elapses. Two consecutive 1-byte
reads are required to get the full 12 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge and
is clocked into the P on SCLK’s rising edge.
The first byte contains a leading 1, and seven bits of con-
version result. The second byte contains the remaining
five bits and three trailing zeros. See Figure 11 for con-
nections and Figure 12 for timing.
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX1240/MAX1241
requires 13 clock cycles from the P to clock out the 12
bits of data with no trailing zeros (Figure 13). The maxi-
mum clock frequency to ensure compatibility with QSPI is
2.097MHz.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines under-
neath the ADC package.
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1F and 4.7F
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. If the power supply is very
noisy, a 10
Ω resistor can be connected as a lowpass filter
to attenuate supply noise (Figure 14).
CS
SCLK
DOUT
I/O
SCK
MISO
+3V
SS
a) SPI
CS
SCLK
DOUT
CS
SCK
MISO
+3V
SS
b) QSPI
MAX1240
MAX1241
MAX1240
MAX1241
MAX1240
MAX1241
CS
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1241
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MAX1240BCSA+ 功能描述:模数转换器 - ADC 12-Bit 73ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32