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| 型号： | MAX1245BCAP+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/21页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SERIAL 20-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 66 |
| 位数： | 12 |
| 采样率（每秒）： | 100k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.4mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
8
_______________________________________________________________________________________
_______________Detailed Description
The MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (Ps). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1F capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acqui-
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on CHOLD as a
sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input, IN+, to the
negative input, IN- (In single-ended mode, IN- is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) -
(VIN-)] from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
|IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ = 9 x (RS + RIN) x 16pF
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
COM
VREF
OUT
REF
CLOCK
1
2
3
4
5
6
7
8
10
11
9
15
16
17
18
19
MAX1245
CS
SHDN
12, 20
14
13
Figure 3. Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
12k
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR
–
+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1245BCAP+ | 功能描述:模数转换器 - ADC 10-Bit 8Ch 100ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1245BCAP+T | 功能描述:模数转换器 - ADC 10-Bit 8Ch 100ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1245BCAP-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1245BCPP | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1245BCPP+ | 功能描述:模数转换器 - ADC 10-Bit 8Ch 100ksps 3.3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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