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参数资料
| 型号： | MAX1247ACEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SERIAL 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 133k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 667mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个差分，单极；2 个差分，双极 |
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
20
______________________________________________________________________________________
At VREF, the DC input resistance is a minimum of 18k
.
During conversion, an external reference at VREF must
deliver up to 350A DC load current and have 10
or
less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7F capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD. In
power-down, the input bias current to REFADJ can be
as much as 25A with REFADJ tied to VDD. Pull
REFADJ to AGND to minimize the input bias current in
power-down.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coeffi-
cient of 4ppm/°C or less to achieve accuracy to within
1LSB over the 0°C to +70°C commercial temperature
range.
Figure 16 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 17 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 610V (2.5V /
4096) for unipolar operation, and 1LSB = 610V [(2.5V /
2 - -2.5V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest-noise
operation, the ground return to the star ground’s power
supply should be low impedance and as short as
possible.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1F and 1F
capacitors close to pin 1 of the MAX1246/MAX1247.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10
resis-
tor can be connected as a lowpass filter (Figure 18).
High-Speed Digital Interfacing with QSPI
The MAX1246/MAX1247 can interface with QSPI using
the circuit in Figure 19 (fSCLK = 2.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the four channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
The MAX1246/MAX1247 are QSPI compatible up to its
maximum external clock frequency of 2MHz.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
12
3
0
(COM)
FS
FS - 3/2LSB
FS = VREF + COM
ZS = COM
INPUT VOLTAGE (LSB)
1LSB =
VREF
4096
Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
UNIPOLAR MODE
BIPOLAR MODE
Full Scale
Zero Scale
Positive
Zero
Negative
Full Scale
Scale
Full Scale
VREF + COM
COM
VREF / 2
COM
-VREF / 2
+ COM
Table 7. Full Scale and Zero Scale
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